Datasheet.kr   

9ZX21901C PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 9ZX21901C
기능 19-Output Differential Zbuffer
제조업체 IDT
로고 IDT 로고 


전체 20 페이지

		

No Preview Available !

9ZX21901C 데이터시트, 핀배열, 회로
19-Output Differential Zbuffer for PCIe Gen2/3
and QPI
9ZX21901C
DATASHEET
General Description
The 9ZX21901 is Intel DB1900Z Differential Buffer suitable for
PCI-Express Gen3 or QPI applications. The part is backwards
compatible to PCIe Gen1 and Gen2. A fixed external feedback
maintains low drift for critical QPI applications. In bypass
mode, the 9ZX21901 can provide outputs up to 400MHz.
Recommended Application
19-output PCIe Gen3/QPI buffer with fixed feedback for
Romley platforms
Output Features
19 – 0.7V current mode differential HCSL output pairs
Key Specifications
Cycle-to-cycle jitter: < 50ps
Output-to-output skew: <65ps
Input-to-output delay: Fixed at 0 ps
Input-to-output delay variation: <50ps
Phase jitter: PCIe Gen3 < 1ps rms
Phase jitter: QPI 9.6GB/s < 0.2ps rms
Features/Benefits
Fixed feedback path/ 0ps input-to-output delay
9 Selectable SMBus addresses; Multiple devices can share
same SMBus segment
8 dedicated OE# pins; hardware control of outputs
PLL or bypass mode; PLL can dejitter incoming clock
Selectable PLL BW; minimizes jitter peaking in downstream
PLL's
Spread spectrum compatible; tracks spreading input clock
for EMI reduction
SMBus Interface; unused outputs can be disabled
100MHz & 133.33MHz PLL mode; legacy QPI support
Undriven differential outputs in Power Down mode for
maximum power savings
Functional Block Diagram
OE(12:5)#
8
DIF_IN
DIF_IN#
Z-PLL
(SS
Compatible)
Bypass path
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
Note: Even though the feedback is fixed, DFB_OUT still
needs a termination network for the part to function.
9ZX21901C REVISION N 11/19/15
1
DFB_OUT
DIF(18:0)
IREF
©2015 Integrated Device Technology, Inc.




9ZX21901C pdf, 반도체, 판매, 대치품
9ZX21901C DATASHEET
Pin Descriptions (cont.)
PIN #
PIN NAME
PIN TYPE
37 OE6#
IN
38 DIF_7
39 DIF_7#
OUT
OUT
40 OE7#
IN
41 DIF_8
42 DIF_8#
OUT
OUT
43 OE8#
IN
44 GND
45 VDD
46 DIF_9
47 DIF_9#
GND
PWR
OUT
OUT
48 OE9#
IN
49 DIF_10
50 DIF_10#
OUT
OUT
51 OE10#
IN
52 DIF_11
53 DIF_11#
OUT
OUT
54 OE11#
IN
55 DIF_12
56 DIF_12#
OUT
OUT
57 OE12#
IN
58 VDD
59 DIF_13
60 DIF_13#
61 DIF_14
62 DIF_14#
63 GND
64 DIF_15
65 DIF_15#
66 DIF_16
67 DIF_16#
68 VDD
69 DIF_17
70 DIF_17#
71 DIF_18
72 DIF_18#
PWR
OUT
OUT
OUT
OUT
GND
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
DESCRIPTION
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 7.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 8.
1 =disable outputs, 0 = enable outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 9.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 10.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 11.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 12.
1 =disable outputs, 0 = enable outputs
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
19-OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI
4
REVISION N 11/19/15

4페이지










9ZX21901C 전자부품, 판매, 대치품
9ZX21901C DATASHEET
Electrical Characteristics – DIF 0.7V Current Mode Differential Outputs
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER
Slew rate
Slew rate matching
Rise/Fall Time Matching
SYMBOL
dV/dt
dV/dt
Trf
CONDITIONS
Scope averaging on
Slew rate matching, Scope averaging on
Rise/fall matching, Scope averaging off
MIN TYP MAX UNITS NOTES
1 2.5 4 V/ns 1, 2, 3
20 % 1, 2, 4
125 ps 1, 7, 8
Voltage High
Voltage Low
VHigh
VLow
Statistical measurement on single-ended signal 660 750 850
using oscilloscope math function. (Scope
mV
averaging on)
-150 150
1
1
Max Voltage
Min Voltage
Vmax
Vmin
Measurement on single ended signal using
absolute value. (Scope averaging off)
-300
1150 mV
1
1
Vswing
Vswing
Scope averaging off
300
mV 1, 2
Crossing Voltage (abs)
Crossing Voltage (var)
Vcross_abs
-Vcross
Scope averaging off
Scope averaging off
250 550 mV 1, 5
140 mV 1, 6
1Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475(1%), IREF = 2.32mA.
IOH = 6 x IREF and VOH = 0.7V @ ZO=50(100differential impedance).
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross
absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
7 Measured from single-ended waveform
8 Measured with scope averaging off, using statistics function. Variation is difference between min and max.
REVISION N 11/19/15
7 19-OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI

7페이지



구       성총 20 페이지
다운로드[ 9ZX21901C.PDF 데이터시트 ]
구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

전력 반도체 판매 ( IGBT, TR 모듈, SCR, 다이오드 모듈 )

휴대전화 : 010-3582-2743


상호 : 아이지 인터내셔날

전화번호 : 051-319-2877, [ 홈페이지 ]



링크공유

링크 :

관련 데이터시트

부품번호상세설명 및 기능제조사
9ZX21901B

19-Output Differential Zbuffer

IDT
IDT
9ZX21901C

19-Output Differential Zbuffer

IDT
IDT

DataSheet.kr    |   2019   |  연락처   |  링크모음   |   검색  |   사이트맵