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부품번호 | 9ZXL0831 기능 |
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기능 | Low-power 8-output differential buffer | ||
제조업체 | IDT | ||
로고 | |||
전체 18 페이지수
8-OUTPUT DB800ZL
DATASHEET
9ZXL0831
General Description
The 9ZXL0831 is a low-power 8-output differential buffer
that meets all the performance requirements of the Intel
DB800ZL specification. It is suitable for PCI-Express
Gen1/2/3 or QPI/UPI applications, and uses a fixed external
feedback to maintain low drift for demanding QPI/UPI
applications.
Recommended Application
Buffer for Romley, Grantley and Purley Servers, SSD drives
and PCIe
Output Features
• 8 - LP-HCSL Output Pairs
Block Diagram
Features/Benefits
• Low-power push-pull outputs; Save power and board
space - no Rp
• Space-saving 48-pin VFQFPN package
• Fixed feedback path for 0ps input-to-output delay
• 8 OE# pins; hardware control of each output
• PLL or bypass mode; PLL can dejitter incoming clock
• 100MHz or 133MHz PLL mode operation; supports PCIe
and QPI applications
• Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible; tracks spreading input
clock for low EMI
Key Specifications
• Cycle-to-cycle jitter <50ps
• Output-to-output skew <65 ps
• Input-to-output delay variation <50ps
• PCIe Gen3 phase jitter <1.0ps RMS
• QPI/UPI 9.6GT/s 12UI phase jitter <0.2ps RMS
OE(7:0)#
DIF_IN
DIF_IN#
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
Logic
SMBDAT
SMBCLK
Z-PLL
(SS Compatible)
DFB_OUT_NC
DIF(7:0)
IDT® 8-OUTPUT DB800ZL
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Pin Descriptions (cont.)
PIN #
PIN NAME
32 DIF_5
33 DIF_5#
34 VDD
35 DIF_6
36 DIF_6#
TYPE
DESCRIPTION
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
PWR Power supply, nominal 3.3V
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
37 vOE6#
Active low input for enabling DIF pair 6. This pin has an internal pull-down.
IN 1 =disable outputs, 0 = enable outputs
38 VDD
39 DIF_7
40 DIF_7#
PWR Power supply, nominal 3.3V
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
41 vOE7#
Active low input for enabling DIF pair 7. This pin has an internal pull-down.
IN 1 =disable outputs, 0 = enable outputs
42 VDD
43 NC
44 VDDA
45 NC
46 NC
47 100M_133M#
48 HIBW_BYPM_LOBW#
49 GND
PWR Power supply, nominal 3.3V
N/A No Connection.
PWR 3.3V power for the PLL core.
N/A No Connection.
N/A No Connection.
3.3V Input to select operating frequency.
IN See Functionality Table for Definition
IN
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
PWR Ground
IDT® 8-OUTPUT DB800ZL
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8-OUTPUT DB800ZL
Electrical Characteristics–DIF 0.7V Low Power Differential Outputs
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
Slew rate
Slew rate matching
Trf
∆Trf
CONDITIONS
Scope averaging on
Slew rate matching, Scope averaging on
MIN TYP MAX UNITS NOTES
2 3.3 4 V/ns 1, 2, 3
6.8 20 % 1, 2, 4
Voltage High
Voltage Low
VHigh
VLow
Statistical measurement on single-ended signal 660 778 850
using oscilloscope math function. (Scope
mV
averaging on)
-150 0 150
1
1
Max Voltage
Min Voltage
Vmax
Vmin
Measurement on single ended signal using
absolute value. (Scope averaging off)
918 1150 mV
-300 -71
1
1
Vswing
Vswing
Scope averaging off
300 1556 1812 mV 1, 2
Crossing Voltage (abs)
Crossing Voltage (var)
Vcross_abs
∆-Vcross
Scope averaging off
Scope averaging off
300 458 550 mV 1, 5
17 140 mV 1, 6
1Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with RS = 27Ω for Zo = 85Ω differential trace
impedance).
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting ∆-Vcross to be smaller than Vcross absolute.
Electrical Characteristics–Current Consumption
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Operating Current
IDDVDD
IDDVDDA
133MHz, VDD rail
133MHz, VDDA + VDDR rail, PLL Mode
Powerdown Current
IDDVDDPD
IDDVDDAPD
Power Down, VDD Rail
Power Down, VDDA Rail
1Guaranteed by design and characterization, not 100% tested in production.
2 CL = 2pF with RS = 27Ω for Zo = 85Ω differential trace impedance
MIN TYP MAX UNITS NOTES
59 75 mA 1
19 25 mA 1
1.2 2 mA 1
2.5 5 mA 1
IDT® 8-OUTPUT DB800ZL
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7페이지 | |||
구 성 | 총 18 페이지수 | ||
다운로드 | [ 9ZXL0831.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
9ZXL0831 | Low-power 8-output differential buffer | IDT |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |