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Número de pieza | 9ZXL1950 | |
Descripción | 19-output DB1900Z Low-Power Derivative | |
Fabricantes | IDT | |
Logotipo | ||
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No Preview Available ! 19-output DB1900Z Low-Power Derivative
w/85ohm Terminations
9ZXL1950
DATASHEET
General Description
The 9ZXL1950 is a DB1900Z derivative buffer utilizing
Low-Power HCSL (LP-HCSL) outputs to increase edge rates
on long traces, reduce board space, and reduce power
consumption more than 50% from the original 9ZX21901.It is
pin-compatible to the 9ZXL1930 and fully integrates the
output terminations. It is suitable for PCI-Express Gen1/2/3 or
QPI/UPI applications, and uses a fixed external feedback to
maintain low drift for demanding QPI/UPI applications.
Recommended Application
Buffer for Romley, Grantley and Purley Servers
Output Features
19 LP-HCSL output pairs w/integrated terminations (Zo =
85
Key Specifications
• Cycle-to-cycle jitter: <50ps
• Output-to-output skew: <50ps
• Input-to-output delay variation: <50ps
• Phase jitter: PCIe Gen3 <1ps rms
• Phase jitter: QPI/UPI 9.6GB/s <0.2ps rms
Features/Benefits
• LP-HCSL outputs; up to 90% IO power reduction, better
signal integrity over long traces
• Direct connect to 85Ω transmission lines; eliminates 76
termination resistors, saves 130mm2 area
• Pin compatible to the 9ZXL1930; easy upgrade to reduced
board space
• 72-pin VFQFPN package; smallest 19-output Z-buffer
• Fixed feedback path; ~0ps input-to-output delay
• 9 Selectable SMBus addresses; multiple devices can share
same SMBus segment
• Separate VDDIO for outputs; allows maximum power
savings
• PLL or bypass mode; PLL can dejitter incoming clock
• 100MHz & 133.33MHz PLL mode; legacy QPI support
• Selectable PLL BW; minimizes jitter peaking in downstream
PLL's
• Spread spectrum compatible; tracks spreading input clock
for EMI reduction
• SMBus Interface; unused outputs can be disabled
Block Diagram
DIF_IN
DIF_IN#
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
Z-PLL
(SS Compatible)
FBOUT_NC
DIF(18:0)
9ZXL1950 REVISION E 11/20/15 1 ©2015 Integrated Device Technology, Inc.
1 page 9ZXL1950 DATASHEET
Electrical Characteristics–Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
3.3V Core Supply Voltage VDDA, R
3.3V Logic Supply Voltage VDD
I/O Supply Voltage
VDDIO
Input Low Voltage
VIL
Input High Voltage
VIH
Except for SMBus interface
Input High Voltage
VIHSMB
SMBus clock and data pins
Storage Temperature
Ts
Junction Temperature
Tj
Input ESD protection ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
MIN
GND-0.5
-65
2000
TYP
UNITS NOTES
MAX
4.6 V 1,2
4.6 V 1,2
4.6 V 1,2
V1
VDD+0.5V
5.5V
V
V
1
1
150 °C 1
125 °C 1
V1
Electrical Characteristics–DIF_IN Clock Input Parameters
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Input Crossover Voltage -
DIF_IN
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
VCROSS
VSWING
dv/dt
Cross Over Voltage
Differential value
Measured differentially
150 900 mV 1
300 mV 1
0.4 8 V/ns 1,2
Input Leakage Current
Input Duty Cycle
IIN
dtin
VIN = VDD , VIN = GND
Measurement from differential wavefrom
-5
45
5 uA
55 % 1
Input Jitter - Cycle to Cycle JDIFIn
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
0
125 ps 1
Electrical Characteristics–Current Consumption
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Operating Supply Current
IDDVDD
IDDVDDA/R
IDDVDDIO
All outputs 100MHz, CL = 2pF; Zo = 85Ω
All outputs 100MHz, CL = 2pF; Zo = 85Ω
All outputs 100MHz, CL = 2pF; Zo = 85Ω
20 35 mA
15 20 mA
142 185 mA
IDDVDDPD
All differential pairs low-low
2.2 6 mA
Powerdown Current
IDDVDDA/RPD
IDDVDDIOPD
All differential pairs low-low
All differential pairs low-low
4.5 9 mA
0.1 1 mA
NOTES
REVISION E 11/20/15
5 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS
5 Page 9ZXL1950 DATASHEET
9ZXL1950 SMBus Addressing
SADR(1:0)_tri
SMBus Address (Rd/Wrt bit = 0)
00 D8
0M DA
01 DE
M0 C2
MM C4
M1 C6
10 CA
1M CC
11 CE
SMBusTable: PLL Mode, and Frequency Select Register
Byte 0 Pin #
Name
Control Function
Bit 7
4
PLL Mode 1
PLL Operating Mode Rd back 1
Bit 6
4
PLL Mode 0
PLL Operating Mode Rd back 0
Bit 5
72/71
DIF_18_En
Output Control
Bit 4
68/67
DIF_17_En
Output Control
Bit 3
66/65
DIF_16_En
Output Control
Bit 2
Reserved
Bit 1
Reserved
Bit 0
3
100M_133M#
Frequency Select Readback
Type
R
R
RW
RW
RW
R
01
See PLL Operating Mode
Readback Table
Low/Low
Enable
Low/Low
Enable
Low/Low
Enable
133MHz
100MHz
Default
Latch
Latch
1
1
1
0
0
Latch
SMBusTable: Output Control Register
Byte 1 Pin #
Name
Bit 7
38/37
DIF_7_En
Bit 6
35/36
DIF_6_En
Bit 5
31/32
DIF_5_En
Bit 4
29/30
DIF_4_En
Bit 3
25/26
DIF_3_En
Bit 2
23/24
DIF_2_En
Bit 1
19/20
DIF_1_En
Bit 0
17/18
DIF_0_En
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Low/Low
1
Enable
Default
1
1
1
1
1
1
1
1
SMBusTable: Output Control Register
Byte 2 Pin #
Name
Bit 7
62/61
DIF_15_En
Bit 6
60/59
DIF_14_En
Bit 5
56/55
DIF_13_En
Bit 4
54/53
DIF_12_En
Bit 3
50/49
DIF_11_En
Bit 2
48/47
DIF_10_En
Bit 1
44/43
DIF_9_En
Bit 0
42/41
DIF_8_En
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Low/Low
1
Enable
Default
1
1
1
1
1
1
1
1
SMBusTable: PLL SW Override Control Register
Byte 3 Pin #
Name
Control Function
Type
0
1 Default
Bit 7
Reserved
0
Bit 6
Reserved
0
Bit 5
Reserved
0
Bit 4
Reserved
0
Bit 3
PLL_SW_EN
Enable S/W control of PLL BW
RW HW Latch SMBus Control 0
Bit 2
PLL Mode 1
PLL Operating Mode 1
RW
See PLL Operating Mode
1
Bit 1
PLL Mode 0
PLL Operating Mode 1
RW
Readback Table
1
Bit 0
Reserved
0
Note: Setting bit 3 to '1' allows the user to overide the Latch value from pin 4 via use of bits 2 and 1. Use the values from the PLL Operating
Mode Readback Table. Note that Byte 0, Bits 7:6 will keep the value originally latched on pin 4. A warm reset of the system will have to
accomplished if the user changes these bits.
REVISION E 11/20/15
11 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS
11 Page |
Páginas | Total 18 Páginas | |
PDF Descargar | [ Datasheet 9ZXL1950.PDF ] |
Número de pieza | Descripción | Fabricantes |
9ZXL1950 | 19-output DB1900Z Low-Power Derivative | IDT |
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