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BVA2140 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 BVA2140
기능 0.7-4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER
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BVA2140 데이터시트, 핀배열, 회로
BVA2140
0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER
Product Description
Figure 2. Package Type
The BVA2140 is a digitally controlled variable gain amplifi-
er (DVGA) in a small 4x4mm QFN package, with a broad-
band frequency range of 700 to 4000 MHz and an oper-
ating VDD of 5.0V at 150mA.
BVA2140 is high performance and high dynamic range
makes it ideally suited for use in WCDMA/LTE wireless
infrastructure point-to-point and other demanding wire-
less applications.
The BVA2140 is an integration of a high performance digi-
tal 6-step attenuator (DSA) that provides a 31.5 dB attenu-
ation range in 0.5 dB steps, and high linearity broadband
gain block amplifiers featuring high ACLR and P1.
The BVA2140 digital control interface supports serial pro-
gramming of the attenuator, and includes the ability to
define the initial attenuation state at power-up.
Implementation requires only a few external components,
such as DC blocking capacitors on the Input and Output
pins, plus a bypass capacitor and a RF choke for the Output
port.
Figure 1. Functional Block Diagram
24-lead 4x4 mm QFN
Device Features
Small 24-Pin 4 x 4 mm QFN Package
Integrate Amp1 to DSA and DSA to Amp2 Functionality
Wide Power supply range of +2.7~5.5V(DSA)
Single Fixed +5.0V supply(Amp)
700-4000MHz Broadband Performance
30.2dB Gain at 2.14GHz (Matching Circuit)
2.9dB Noise Figure at max gain setting at 2.14GHz(Matching Circuit)
25.1dBm P1dB at 2.14GHz (Matching Circuit)
40dBm OIP3 at 2.14GHz(10dBm per tone, Matching Circuit)
15.2dBm LTE 20MHz ACLR at 1.9GHz (FDD E-TM1.1, 20MHz BW, ±20MHz
offset, PAR 9.81 at 0.01% Prob. , –50dBc)
Attenuation: 0.5 dB steps to 31.5 dB
Safe attenuation state transitions
Monotonicity: 0.5 dB up to 4 GHz
High attenuation accuracy(DSA to Amp)
±(0.3dB + 5% x Atten) @ 0.7~4GHz
1.8V control logic compatible
Programming modes
- Serial
Unique power-up state selection
18 17 16 15 14 13
VSS/GND 19
P/S 20
DSAIN 21
GND 22
AMP1OUT 23
GND 24
DSA
AMP1
AMP2
123456
12 CLOCK
11 DATA
10 DSAOUT
9 GND
8 AMP2IN
7 GND
Application
Base station/Repeater Infrastructure
LTE/WCDMA/CDMA Wireless infrastructure and other high performance RF
application
Commercial/Industrial/Military Wireless system
General purpose Wireless
BeRex
●website: www.berex.com
●email: sales@berex.com
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
1
Rev. 0.1




BVA2140 pdf, 반도체, 판매, 대치품
BVA2140
0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER
Programming mode
Table 5. PUP Truth Table
Serial Interface
The serial interface is a 6-bit serial-in, parallel-out
shift register buffered by a transparent latch. It is
controlled by three CMOS-compatible signals: Data, Clock, and Latch
Enable (LE). The Data and Clock
inputs allow data to be serially entered into the shift
register, a process that is independent of the state of
the LE input.
The LE input controls the latch. When LE is HIGH,
the latch is transparent and the contents of the serial
shift register control the attenuator. When LE is
brought LOW, data in the shift register is latched.
The shift register should be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data. The timing for this operation is defined by
Figure 3 (Serial Interface Timing Diagram) and
Table 6 (Serial Interface AC Characteristics).
Power-up Control Settings
The BVA2140 always assumes a specifiable attenuation setting on
power-up. This feature exists for Parallel modes of operation, and
allows a known attenuation state to be established before an initial
serial or parallel control word is provided.
When the attenuator powers up in LE=1 or P/S = 1, PUP1 and PUP2
are not active. But When the attenuator powers up in P/S = 0 with LE
= 0, the control bits are automatically set to one of four possible
values.
These four values are selected by the two power-up
control bits, PUP1 and PUP2, as shown in Table 5
(Power-Up Truth Table).
P/S LE PUP2 PUP1
Attenuation state
0000
Reference Loss
0010
8 dB
0001
16 dB
0011
31.5 dB
0 1 X X Defined by C0.5-C16
Note: If Power up with LE = 1 or P/S=1, PUP1 and PUP2 are not active
Figure 3. Serial Interface Timing Diagram
Table 6. Serial Interface AC Characteristics
VDD = 5.0V with DSA only, -40°C < TA < 105°C, unless otherwise specified
Symbol
Parameter
fClk Serial data clock frequency
Min Max Unit
10 MHz
tClkH Serial clock HIGH time
30 ns
tClkL Serial clock LOW time
tLESUP
LE set-up time after last
clock falling edge
tLEPW LE minimum pulse width
tSDSUP
Serial data set-up time
before clock rising edge
tSDHLD
Serial data hold time after
clock falling edge
30 ns
10 ns
30 ns
10 ns
10 ns
Note: fClk is verified during the functional pattern test. Serial programming sections of the functional pattern
are clocked at 10 MHz to verify fclk specification
Table 7. 6-Bit Attenuator Serial Programming
B5 B4 B3 B3 B1 B0
C16 C8 C4 C2 C1 C0.5
MSB (first in)
LSB (Last in)
BeRex
●website: www.berex.com
●email: sales@berex.com
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
4
Rev. 0.1

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BVA2140 전자부품, 판매, 대치품
BVA2140
0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER
Typical RF Performance Plot - BVA2140 EVK - PCB(700MHz Application Circuit)
Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit
Table 10. Typical Performance : 700MHz
Figure 5. Gain vs Frequency @Max Gain state
parameter
Frequency
Gain
S11
S22
S12
OIP31
P1dB
Noise Figure
LTE20MHz ACLR2
Typical Values
700
41
-24.1
-8.9
-52.2
45
25.7
2.6
15.4
Units
MHz
dB
dB
dB
dB
dBm
dBm
dB
dBm
1
OIP3 _ measured with two tones at an output of 10 dBm per tone separated by 1 MHz.
2
LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. @ACLR –50dBc .
Figure 6. Input Return Loss vs Frequency
@Max Gain & Min Gain state
Figure 7. Output Return Loss vs Frequency
@Max Gain & Min Gain state
Figure 8. Attenuation Error vs Attenuation
Setting @700MHz
Figure 9. Attenuation Error vs Frequency
@Major Attenuation Steps
Note: Upper Limit & Lower Limit is the value converted to a graph 0.3dB+0.5%
BeRex
●website: www.berex.com
●email: sales@berex.com
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
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BVA2140

0.7-4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER

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