PDF EM6AB080 Data sheet ( Hoja de datos )

Número de pieza	EM6AB080
Descripción	64M x 8 bit DDR Synchronous DRAM
Fabricantes	Etron Technology
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No Preview Available ! EtronTech EM6AB080 Etron Confidential 64M x 8 bit DDR Synchronous DRAM (SDRAM) Advanced (Rev. 1.1, Dec. /2013) Features • Fast clock rate: 250/200MHz • Differential Clock CK & CK • Bi-directional DQS • DLL enable/disable by EMRS • Fully synchronous operation • Internal pipeline architecture • Four internal banks, 16M x 8-bit for each bank • Programmable Mode and Extended Mode registers - CAS Latency: 2, 2.5, 3 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleaved • Individual byte write mask control • DM Write Latency = 0 • Auto Refresh and Self Refresh • 8192 refresh cycles / 64ms • Precharge & active power down • Power supplies: VDD & VDDQ = 2.5V 0.2V • Interface: SSTL_2 I/O Interface • Package: 66 Pin TSOP II, 0.65mm pin pitch - Pb and Halogen free • Package: 60-Ball, 8x13x1.2 mm (max) TFBGA - Pb free and Halogen Free Overview The EM6AB080 SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 512 Mbits. It is internally configured as a quad 16M x 8-bit DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and CK . Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The EM6AB080 provides programmable Read or Write burst lengths of 2, 4, or 8. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, EM6AB080 features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth, result in a device particularly well suited to high performance main memory and graphics applications. Table 1.Ordering Information Part Number Clock Frequency Data Rate EM6AB080TSB-4G 250MHz 500Mbps/pin EM6AB080TSB-5G 200MHz 400Mbps/pin EM6AB080WKB-4H 250MHz 500Mbps/pin EM6AB080WKB-5H 200MHz 400Mbps/pin TS: indicates TSOPII package WK: indicates TFBGA package B: indicates Generation Code G: indicates Pb free and Halogen Free for TSOPII Package H: indicates Pb free and Halogen Free for TFBGA Package Package TSOPII TSOPII TFBGA TFBGA Etron Technology, Inc. No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc. reserves the right to change products or specification without notice. 1 page EtronTech EM6AB080 VDDQ VSSQ VREF NC Supply DQ Power: 2.5V 0.2V. Provide isolated power to DQs for improved noise immunity. Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. Supply SSTL_2 reference Voltage - No Connect: These pins should be left unconnected. Etron Confidential 5 Rev.1.1 Dec. /2013 5 Page EtronTech EM6AB080 Table 15. D.C. Characteristics (VDD = 2.5V ± 0.2V, TA = 0~70 °C) Parameter & Test Condition Symbol OPERATING CURRENT: One bank; Active-Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles. OPERATING CURRENT: One bank; BL=4; reads - Refer to the following page for detailed test conditions PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; power-down mode; tCK=tCK(min); CKE = LOW PRECHARGE FLOATING STANDBY CURRENT: CS = HIGH; all banks idle; CKE = HIGH; tCK =tCK(min); address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM PRECHARGE QUIET STANDBY CURRENT: CS =HIGH; all banks idle; CKE =HIGH; tCK=tCK(min) address and other control inputs stable at ≥ VIH(min) or ≤ VIL (max); VIN = VREF for DQ, DQS and DM ACTIVE POWER-DOWN STANDBY CURRENT : one bank active; power-down mode; CKE=LOW; tCK=tCK(min) ACTIVE STANDBY CURRENT : CS =HIGH;CKE=HIGH; one bank active ; tRC=tRC(max);tCK=tCK(min);Address and control inputs changing once per clock cycle; DQ,DQS,and DM inputs changing twice per clock cycle OPERATING CURRENT BURST READ : BL=2; READS; Continuous burst; one bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); lout=0mA;50% of data changing on every transfer OPERATING CURRENT BURST Write : BL=2; WRITES; Continuous Burst ;one bank active; address and control inputs changing once per clock cycle; tCK=tCK(min); DQ,DQS,and DM changing twice per clock cycle; 50% of data changing on every transfer AUTO REFRESH CURRENT : tRC=tRFC(min); tCK=tCK(min) SELF REFRESH CURRENT: Self Refresh Mode ; CKE 0.2V;tCK=tCK(min) BURST OPERATING CURRENT 4 bank operation: Four bank interleaving READs; BL=4;with Auto Precharge; tRC=tRC(min); tCK=tCK(min); Address and control inputs change only during Active, READ , or WRITE command IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 -4 -5 Max. Unit 85 80 mA 95 90 mA 5 5 mA 40 35 mA 40 35 mA 20 20 mA 65 65 mA 150 130 mA 150 130 mA 160 140 mA 6 6 mA 230 210 mA Etron Confidential 11 Rev.1.1 Dec. /2013 11 Page

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