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PDF MAX11156 Data sheet ( Hoja de datos )
| Número de pieza | MAX11156 | |
| Descripción | SAR ADC | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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EVALUATION KIT AVAILABLE
MAX11156
18-Bit, 500ksps, ±5V SAR ADC
with Internal Reference in TDFN
General Description
The MAX11156 18-bit, 500ksps, SAR ADC offers excellent
AC and DC performance with true bipolar input range,
small size, and internal reference. The MAX11156 measures
a ±5V (10VP-P) input range while operating from a
single 5V supply. A patented charge-pump architecture
allows direct sampling of high-impedance sources. The
MAX11156 integrates an optional internal reference and
buffer, saving additional cost and space.
This ADC achieves 94.6dB SNR and -101.4dB THD (typ).
The MAX11156 guarantees 18-bit no-missing codes and
±2.8 LSB INL (typ).
The MAX11156 communicates using an SPI-compatible
serial interface at 2.5V, 3V, 3.3V, or 5V logic. The serial
interface can be used to daisy-chain multiple ADCs in
parallel for multichannel applications and provides a busy
indicator option for simplified system synchronization and
timing.
The MAX11156 is offered in a 12-pin, 3mm x 3mm,
TDFN package and is specified over the -40°C to +85°C
temperature range.
Applications
● Data Acquisition Systems
● Industrial Control Systems/Process Control
● Medical Instrumentation
● Automatic Test Equipment
Selector Guide and Ordering Information appear at end of
data sheet.
Typical Operating Circuit
10Ω
±5V
MAX9632
4.7nF
AIN+
AIN-
REF
10µF
1µF VDD
(5V)
18-BIT ADC
MAX11156
REF
BUF
AGNDS
1µF OVDD
(2.3V TO 5V)
INTERFACE
AND CONTROL
CONFIGURATION REGISTER
INTERNAL REFERENCE
SCLK
DIN
DOUT
CNVST
HOST
CONTROLLER
REFIO
GND 0.1µF
Benefits and Features
● High DC/AC Accuracy Improves Measurementuality
• 18-Bit Resolution with No Missing Codes
• 500ksps Throughput Rate Without Pipeline Delay/
Latency
• 94.6dB SNR and -101.4dB THD at 10kHz
• 1.6 LSBRMS Transition Noise
• ±0.5 LSB DNL (typ) and ±2.8 LSB INL (typ)
● Highly Integrated ADC Saves Cost and Space
• 6ppm/°C (typ) Internal Reference
• Internal Reference Buffer
• ±5V Bipolar Analog Input Range
● Wide Supply Range and Low Power Simplify
Power-Supply Design
• 5V Analog Supply
• 2.3V to 5V Digital Supply
• 25.8mW Power Consumption at 500ksps
• 10µA in Shutdown Mode
● Multi-Industry Standard Serial Interface and
Small Package Reduce Size
• SPI/QSPI™/MICROWIRE®/DSP-Compatible Serial
Interface
• 3mm x 3mm Tiny 12-Pin TDFN Package
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corporation.
14-Bit to 18-Bit SAR ADC Family
14-BIT
16-BIT
500ksps 250ksps
16-BIT
500ksps
18-BIT
500ksps
±5V Input
Internal
Reference
0 to 5V Input
Internal
Reference
—
—
MAX11167 MAX11166 MAX11156
MAX11169 MAX11168 MAX11158
MAX11161 MAX11160 MAX11150
MAX11165 MAX11164 MAX11154
0 to 5V Input
External MAX11262 MAX11163 MAX11162 MAX11152
Reference
19-6622; Rev 2; 10/15
1 page  
MAX11156
18-Bit, 500ksps, ±5V SAR ADC
with Internal Reference in TDFN
Electrical Characteristics (continued)
(VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 500ksps, VREF = 4.096V, Reference Mode 3; TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER
Output Voltage Low
Three-State Leakage Current
Three-State Output Capacitance
TIMING (Note 9)
Time Between Conversions
Conversion Time
Acquisition Time
CNVST Pulse Width
SCLK Period (CS Mode)
SCLK Period (Daisy-Chain
Mode)
SCLK Low Time
SCLK High Time
SCLK Falling Edge to Data Valid
Delay
CNVST Low to DOUT D15 MSB
Valid (CS Mode)
CNVST High or Last SCLK
Falling Edge to DOUT High
Impedance
SYMBOL
VOL
tCYC
tCONV
tACQ
tCNVPW
tSCLK
tSCLK
tSCLKL
tSCLKH
tDDO
tEN
tDIS
CONDITIONS
ISINK = 2mA
CNVST rising to data available
tACQ = tCYC - tCONV
CS mode
VOVDD > 4.5V
VOVDD > 2.7V
VOVDD > 2.3V
VOVDD > 4.5V
VOVDD > 2.7V
VOVDD > 2.3V
VOVDD > 4.5V
VOVDD > 2.7V
VOVDD > 2.3V
VOVDD > 2.7V
VOVDD < 2.7V
CS Mode
MIN
-10
2
1.35
0.5
5
14
20
26
16
24
30
5
5
TYP
15
MAX
0.4
+10
UNITS
V
µA
pF
100000
1.5
µs
µs
µs
ns
ns
ns
ns
ns
12
18 ns
23
14
ns
17
20 ns
DIN Valid Setup Time from SCLK
Falling Edge
tSDINSCK
DIN Valid Hold Time from SCLK
Falling Edge
tHDINSCK
VOVDD > 4.5V
VOVDD > 2.7V
VOVDD > 2.3V
3
5
6
0
ns
ns
SCLK Valid Setup Time to
CNVST Falling Edge
tSSCKCNF
3 ns
SCLK Valid Hold Time to CNVST
Falling Edge
tHSCKCNF
6 ns
www.maximintegrated.com
Maxim Integrated │ 5
5 Page 
MAX11156
Functional Diagram
AIN+
AIN-
AGNDS
18-BIT ADC
MAX11156
INTERFACE
AND CONTROL
CONFIGURATION REGISTER
REFIO
INTERNAL
REFERENCE
10kΩ
SW1
SW2
REF
BUF
18-Bit, 500ksps, ±5V SAR ADC
with Internal Reference in TDFN
DIN
SCLK
DOUT
CNVST
VDD
OVDD
GND
REF
CONFIGURATION
REGISTER
B5 B4
00
01
10
11
REFERENCE SWITCH
REFERENCE
STATE
MODE SW2 SW1
0 CLOSED CLOSED
1 CLOSED OPEN
2 OPEN CLOSED
3 OPEN OPEN
Detailed Description
The MAX11156 is an 18-bit single-channel, pseudo-
differential ADC with a maximum throughput rates of
500ksps. This ADC includes a precision internal reference
that allows for measuring a bipolar input voltage range of
Q5V. Input ranges of ±3.05V to ±5.19V can be obtained by
applying external reference. Both inputs (AIN+ and AIN-)
are sampled with a pseudo-differential on-chip track-and-
hold exhibiting no pipeline delay or latency, making these
ADCs ideal for multiplexed applications.
The MAX11156 measures a true bipolar voltage of Q5V
(10VP-P) and the inputs are protected for up to Q20mA of
overrange current. This ADC is powered from a 4.75V to
5.25V analog supply (VDD) and a separate 2.3V to 5.25V
digital supply (OVDD). The MAX11156 requires 500ns to
acquire the input sample on an internal track-and-hold
and then convert the sampled signal to 18 bits of accuracy
using an internally clocked converter.
Analog Inputs
The MAX11156 ADC consists of a true sampling pseudo-
differential input stage with high-impedance, capacitive
inputs. The internal T/H circuitry feature a small-signal
bandwidth of about 6MHz to provide 18-bit accurate
sampling in 500ns. This allows for accurate sampling of a
number of scanned channels through an external multiplexer.
The MAX11156 can thus convert input signals on AIN+ in
the range of -(K O VREF + AIN-) to +(K O VREF + AIN-)
where K = 5.000/4.096. AIN+ should also be limited to
±(VDD + 0.1V) for accurate conversions. AIN- has an input
range of -0.1V to +0.1V and should be connected to the
ground reference of the input signal source. The MAX11156
performs a true differential sample on inputs between AIN+
and AIN- with good common-mode rejection (see the Typical
Operating Circuit). This allows for improved sampling of
remote transducer inputs.
Many traditional ADCs with single supplies that
measure bipolar input signals use resistive divider
networks directly on the analog inputs. These networks
increase the complexity of the input signal conditioning.
However, the MAX11156 includes a patented input switch
architecture which allows direct sampling onto the input
sample and hold capacitor without the use of scaling
resistor networks. This results in zero source loading
errors when the sample and hold is allowed to fully settle.
This architecture requires a minimum sample rate of
10Hz to maintain accurate conversions over the designed
temperature and supply ranges.
www.maximintegrated.com
Maxim Integrated │ 11
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet MAX11156.PDF ] | |
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