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PDF 831724 Data sheet ( Hoja de datos )
| Número de pieza | 831724 | |
| Descripción | Differential Clock/Data Multiplexer | |
| Fabricantes | IDT | |
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Differential Clock/Data Multiplexer
831724
Datasheet
General Description
The 831724 is a high-performance, differential HCSL clock/data
multiplexer and fanout buffer. The device is designed for the
multiplexing and fanout of high-frequency clock and data signals.
The device has two differential, selectable clock/data inputs. The
selected input signal is distributed to four low-skew differential HCSL
outputs. Each input pair accepts HCSL, LVDS and LVPECL levels.
The 831724 is characterized to operate from a 3.3V power supply.
Guaranteed input, output-to-output and part-to-part skew
characteristics make the 831724 ideal for those clock and data
distribution applications demanding well-defined performance and
repeatability. The 831724 supports the clock multiplexing and
distribution of PCI Express Generation 1, 2, and 3 clock signals.
Features
• 2:1 differential clock/data multiplexer with fanout
• Two selectable, differential inputs
• Each differential input pair can accept the following levels: HCSL,
LVDS, LVPECL.
• Four differential HCSL outputs
• Maximum input/output clock frequency: 350MHz
• Maximum input/output data rate: 700Mb/s (NRZ)
• LVCMOS interface levels for all control inputs
• PCI Express Gen 1,2,3 jitter compliant
• Input skew: 165ps (maximum)
• Output skew: 175ps (maximum)
• Part-to-part skew: 450ps (maximum)
• Full 3.3V supply voltage
• Available in lead-free (RoHS 6) package
• -40°C to 85°C ambient operating temperature
Block Diagram
IREF
Pulldown
CLK0 Pullup/down
nCLK0 Pulldown
Pullup/down
CLK1
nCLK1 Pulldown
Pullup
Pullup
Pullup
Pullup
SEL
0
1
QA
nQA
QB
nQB
QC
nQC
QD
nQD
Pin Assignment
32 31 30 29 28 27 26 25
VDD 1
24 nc
nOED 2
23 nOEC
CLK0 3
22 nc
nCLK0 4
21 nc
CLK1 5
20 nc
nCLK1 6
19 nc
nOEA 7
18 SEL
VDD 8
17 nc
9 10 11 12 13 14 15 16
831724I
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision B November 16, 2016
1 page  
831724 Datasheet
AC Electrical Characteristics
Table 5A. PCI Express Jitter Specifications, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Symbol
tj
(PCIe Gen 1)
Parameter
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
tREFCLK_HF_RMS Phase Jitter RMS;
(PCIe Gen 2) NOTE 2, 4
tREFCLK_LF_RMS Phase Jitter RMS;
(PCIe Gen 2) NOTE 2, 4
tREFCLK_RMS
(PCIe Gen 3)
Phase Jitter RMS;
NOTE 3, 4
Test Conditions
ƒ = 100MHz,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
ƒ = 100MHz,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
ƒ = 100MHz,
Low Band: 10kHz - 1.5MHz
ƒ = 100MHz,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
Minimum Typical
11.48
0.76
0.15
0.16
Maximum
27
1.0
1.3
0.4
PCIe Industry
Specification Units
86 ps
3.1 ps
3.0 ps
0.8 ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. The phase noise is dependent on the input signal source. The input signal was generated using a
Tektronix HFS9000 Stimulus System. For additional information, refer to the PCI Express Application Note section in the datasheet.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 106 clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High
Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
©2016 Integrated Device Technology, Inc
5
Revision B November 16, 2016
5 Page 
Parameter Measurement Information, continued
Spectrum of Output Signal Q
A0 MUX selects active
input clock signal
MUX_ISOL = A0 – A1
A1
L or H
SEL
MUX selects static input
Q
MUX Isolation
ƒ
(fundamental)
Frequency
831724 Datasheet
©2016 Integrated Device Technology, Inc
11
Revision B November 16, 2016
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet 831724.PDF ] | |
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