83918 Datasheet PDF ( Pinout ) - 1:18 Crystal-to-LVCMOS/LVTTL Fanout Buffer

83918 Datasheet PDF - IDT

Part Number	*83918*
Description	1:18 Crystal-to-LVCMOS/LVTTL Fanout Buffer
Manufacturers	IDT
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Low Skew, 1:18

Crystal-to-LVCMOS/LVTTL Fanout Buffer

83918

Data Sheet

General Description

The 83918 is a low skew, 1:18 Crystal-to- LVCMOS/LVTTL Fanout

Buffer. The 83918 has selectable LVCMOS/LVTTL clock or crystal

inputs. The low impedance LVCMOS/LVTTL outputs are designed to

drive 50 series or parallel terminated transmission lines.

The 83918 is characterized at full 3.3V, full 2.5V and mixed

3.3V/2.5V, 3.3V/1.8V, and 2.5V/1.8V output operating supply modes.

Guaranteed output and part-to-part skew characteristics make the

83918 ideal for those clock distribution applications demanding well

defined performance and repeatability.

Features

• Eighteen LVCMOS/LVTTL output

• Selectable crystal oscillator interface or LVCMOS_CLK

• Maximum output frequency: 200MHz

• Crystal input frequency range: 10MHz to 40MHz

• RMS phase jitter using a 25MHz crystal (1kHz – 1MHz): 0.449ps

(typical) @ 3.3V/3.3V

• Output skew: 75ps (maximum) @ 3.3V/3.3V

• Operating supply modes:

Core/Output

3.3V/3.3V

3.3V/2.5V

3.3V/1.8V

2.5V/2.5V

2.5V/1.8V

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package

Block Diagram

CLK_SEL Pulldown

XTAL_IN

XTAL_OUT

OSC

LVCMOS_CLK Pulldown

Q0:Q17

Pin Assignment

GND

LVCMOS_CLK

CLK_SEL

XTAL_IN

XTAL_OUT

VDD

VDDO

32 31 30 29 28 27 26 25

1 24

2 23

3 22

4 21

5 20

6 19

7 18

8 17

9 10 11 12 13 14 15 16

VDDO

Q10

Q11

GND

83918

32 Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

Revision B March 17, 2016

83918 Data Sheet

AC Electrical Characteristics

Table 5A. AC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C

Symbol Parameter

Test Conditions

fOUT

tpLH

Output Frequency

Propagation Delay, Low to High;

NOTE 1

tjit(Ø)

RMS Phase Jitter, (Random);

NOTE 2

25MHz,

Integration Range: 1kHz to 1MHz

tjit

Additive Phase Jitter, RMS; refer

to Additive Phase Jitter Section

155.52MHz,

Integration Range: 12kHz to 20MHz

tsk(o)

Output Skew; NOTE 3, 6

tsk(pp) Part-to-Part Skew; NOTE 4, 6

tR / tF

odc

Output Rise/Fall Time; NOTE 5

Output Duty Cycle

20% to 80%

ƒOUT  150MHz

Minimum

1.85

300

Typical

0.449

0.145

Maximum

200

3.0

800

700

Units

MHz

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

All parameters measured at fOUT unless noted otherwise.

NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.

NOTE 2: Refer to the Phase Noise Plot following this section.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.

NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.

NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.

Revision B March 17, 2016

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83918 Datasheet PDF - IDT

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