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부품번호 | 8732-01 기능 |
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기능 | Low Skew 3.3V LVPECL Clock Generator | ||
제조업체 | IDT | ||
로고 | |||
전체 17 페이지수
Low Voltage, Low Skew
3.3V LVPECL Clock Generator
8732-01
Data Sheet
GENERAL DESCRIPTION
The 8732-01 is a low voltage, low skew, 3.3V LVPECL Clock
Generator. The 8732-01 has two selectable clock inputs. The
CLK0, nCLK0 pair can accept most standard differential input
levels.The single ended clock input accepts LVCMOS or LVTTL
input levels. The 8732-01 has a fully integrated PLL along with
frequency configurable outputs. An external feedbackinput and
outputs regenerate clocks with “zero delay”.
The 8732-01 has multiple divide select pins for each bank of
outputs along with 3 independent feedback divide select pins
allowing the 8732-01 to function both as a frequency multiplier
and divider. The PLL_SEL input can be usedto bypass the
PLL for test and system debug purposes.In bypass mode,
the input clock is routed around the PLLand into the internal
output dividers.
Features
• Ten differential 3.3V LVPECL outputs
• Selectable differential CLK0, nCLK0 or
LVCMOS/LVTTL CLK1 inputs
• CLK0, nCLK0 supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• CLK1 accepts the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 350MHz
• VCO range: 250MHz to 700MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Cycle-to-cycle jitter: CLK0, nCLK0, 50ps (maximum)
CLK1, 80ps (maximum)
• Output skew: 150ps (maximum)
• Static phase offset: -150ps to 150ps
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
VCCO
QA0
52 51 50 49 48 47 46 45 44 43 42 41 40
1 39
2 38
VCCO
nQB3
nQA1
VEE
PLL_SEL
VCCO
nQA2
QA3
nQA3
VEE
5 35
6 34
7
ICS8732-01
33
31
10 30
11 29
12 28
13 27
14 15 16 17 18 19 20 21 22 23 24 25 26
QB2
VEE
MR
VCCO
QB1
nQB0
QB0
VEE
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
©2016 Integrated Device Technology, Inc
1
Revision E January 22, 2016
8732-01 Data Sheet
TABLE 3C. CONTROL INPUT FUNCTION TABLE FOR QFB0, QFB1
Inputs
MR PLL_SEL FBDIV_SEL2 FBDIV_SEL1 FBDIV_SEL0
1X
X
X
X
01
0
0
0
01
0
0
1
01
0
1
0
01
0
1
1
01
1
0
0
01
1
0
1
01
1
1
0
01
1
1
1
00
0
0
0
00
0
0
1
00
0
1
0
00
0
1
1
00
1
0
0
00
1
0
1
00
1
1
0
00
1
1
1
Outputs
QFB0, QFB1
nQFB0, nQFB1
Low
fVCO/4
fVCO/6
fVCO/8
fVCO/10
fVCO/8
fVCO/12
fVCO/16
fVCO/20
fREF_CLK/4
fREF_CLK/6
fREF_CLK/8
fREF_CLK/10
fREF_CLK/8
fREF_CLK/12
fREF_CLK/16
fREF_CLK/20
TABLE 4A. QX OUTPUT FREQUENCY W/FB_IN = QFB0 OR QFB1
Inputs
fVCO
FB_IN FBDIV_SEL2 FBDIV_SEL1 FBDIV_SEL0
QFB
0
0
0
QFB
0
0
1
Output Divider Mode
÷4
÷6
CLK1 (MHz)
Minimum Maximum
62.5
175
(NOTE 2)
41.67
116.67
(NOTE 1)
fREF_CLK x 4
fREF_CLK x 6
QFB
0
1
0
÷8
31.25
87.5 fREF_CLK x 8
QFB
0
1
1
÷10 25 70 fREF_CLK x 10
QFB
1
0
0
÷8 31.25
QFB
1
0
1
÷12 20.83
QFB
1
1
0
÷16 15.62
QFB
1
1
1
÷20 12.5
NOTE 1: VCO frequency range is 250MHz to 700MHz.
NOTE 2: The maximum input frequency that the phase detector can accept is 175MHz.
87.5
58.33
43.75
35
fREF_CLK x 8
fREF_CLK x 12
fREF_CLK x 16
fREF_CLK x 20
©2016 Integrated Device Technology, Inc
4
Revision E January 22, 2016
4페이지 PARAMETER MEASUREMENT INFORMATION
8732-01 Data Sheet
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
STATIC PHASE OFFSET
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
©2016 Integrated Device Technology, Inc
7
Revision E January 22, 2016
7페이지 | |||
구 성 | 총 17 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
8732-01 | Low Skew 3.3V LVPECL Clock Generator | IDT |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |