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87972I-147 데이터시트 PDF




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부품번호 87972I-147 기능
기능 1-to-12 LVCMOS/LVTTL Clock Multiplier/Zero Delay Buffer
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87972I-147 데이터시트, 핀배열, 회로
Low Skew, 1-to-12 LVCMOS/LVTTL
Clock Multiplier/Zero Delay Buffer
87972I-147
Datasheet
General Description
The 87972I-147 is a low skew, LVCMOS/LVTTL Clock Generator
and a member of the family of High Performance Clock Solutions
from IDT. The 87972I-147 has three selectable inputs and
provides 14 LVCMOS/LVTTL outputs.
The 87972I-147 is a highly flexible device. Using the crystal
oscillator input, it can be used to generate clocks for a system. All
of these clocks can be the same frequency or the device can be
configured to generate up to three different frequencies among the
three output banks. Using one of the single ended inputs, the
87972I-147 can be used as a zero delay buffer/multiplier/ divider in
clock distribution applications.
The three output banks and feedback output each have their own
output dividers which allows the device to generate a multitude of
different bank frequency ratios and output-to-input frequency
ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be select-
ed to be inverting or non-inverting. The output frequency range is
10MHz to 150MHz. Input frequency range is 6MHz to 150MHz.
The 87972I-147 also has a QSYNC output which can be used or
system synchronization purposes. It monitors Bank A and Bank C
outputs and goes low one period of the faster clock prior to
coincident rising edges of Bank A and Bank C clocks. QSYNC
then goes high again when the coincident rising edges of Bank A
and Bank C occur. This feature is used primarily in applications
where Bank A and Bank C are running at different frequencies,
and is particularly useful when they are running at non-integer
multiples of one another.
Example Applications:
1.System Clock generator: Use a 16.66 MHz Crystal to generate
eight 33.33MHz copies for PCI and four 100MHz copies for the
CPU or PCI-X.
2.Line Card Multiplier: Multiply 19.44MHz from a back plane to
77.76MHz for the line Card ASICs and Serdes.
3.Zero Delay buffer for Synchronous memory: Fan out up to
twelve 100MHz copies from a memory controller reference
clock to the memory chips on a memory module with zero delay.
Features
Fully integrated PLL
Fourteen LVCMOS/LVTTL outputs; (12)clocks, (1)feedback,
(1)sync
Selectable crystal oscillator interface or LVCMOS/LVTTL
reference clock inputs
CLK0, CLK1 can accept the following input levels:
LVCMOS or LVTTL
Output frequency range: 10MHz to 150MHz
VCO range: 240MHz to 500MHz
Output skew: 200ps (maximum)
Cycle-to-cycle jitter, (all banks ÷4): 55ps (maximum)
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Compatible with PowerPC™and Pentium™Microprocessors
Available in lead-free (RoHS 6)packages.
Pin Assignment
39 38 37 36 35 34 33 32 31 30 29 28 27
FSEL_B1
FSEL_B0
FSEL_A1
FSEL_A0
QA3
VDDO
QA2
GNDO
QA1
VDDO
QA0
GNDO
VCO_SEL
40
41
42
43
44
45
46
47
48
49
50
51
52
1
26
25
24
23
22
21
20
19
18
17
16
15
14
2 3 4 5 6 7 8 9 10 11 12 13
FSEL_FB1
QSYNC
GNDO
QC0
VDDO
QC1
FSEL_C0
FSEL_C1
QC2
VDDO
QC3
GNDO
INV_CLK
©2015 Integrated Device Technology, Inc
87972I-147
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y Package
Top View
1 December 7, 2015




87972I-147 pdf, 반도체, 판매, 대치품
87972I-147 Datasheet
Table 1. Pin Descriptions
Number
1
2
3
4
5,
26,
27
6
7
8
9, 10
11,
12
13
14
15, 24, 30,
35, 39, 47,
51
16, 18,
21, 23
17, 22, 33,
37, 45, 49
19,
20
25
28
29
31
32, 34,
36, 38
40,
41
42,
43
44, 46
48, 50
52
Name
GNDI
nMR/OE
FRZ_CLK
FRZ_DATA
FSEL_FB2,
FSEL_FB1,
FSEL_FB0
PLL_SEL
REF_SEL
CLK_SEL
CLK0, CLK1
XTAL_1,
XTAL_2
VDDA
INV_CLK
GNDO
QC3, QC2,
QC1, QC0
VDDO
FSEL_C1,
FSEL_C0
QYSNC
VDD
QFB
EXT_FB
QB3, QB2,
QB1, QB0
FSEL_B1,
FSEL_B0
FSEL_A1,
FSEL_A0
QA3, QA2,
QA1, QA0
VCO_SEL
Type
Power
Input Pullup
Input
Input
Pullup
Pullup
Input Pullup
Input Pullup
Input Pullup
Input
Input
Input
Power
Input
Pullup
Pullup
Pullup
Power
Output
Power
Input Pullup
Output
Power
Output
Input
Output
Pullup
Input Pullup
Input Pullup
Output
Input Pullup
Description
Power supply ground.
Master reset and output enable. When HIGH, enables the outputs.
When LOW, resets the outputs to Hi-Z and resets output divide circuitry.
Enables and disables all outputs. LVCMOS / LVTTL interface levels.
Clock input for freeze circuitry. LVCMOS / LVTTL interface levels.
Configuration data input for freeze circuitry. LVCMOS / LVTTL interface levels.
Select pins control Feedback Divide value. LVCMOS / LVTTL interface levels.
See Table 3B.
Selects between the PLL and reference clocks as the input to the output dividers.
When HIGH, selects PLL. When LOW, bypasses the PLL and reference clocks.
LVCMOS / LVTTL interface levels.
Selects between crystal and reference clock. When LOW, selects CLK0 or CLK1.
When HIGH, selects crystal inputs. LVCMOS / LVTTL interface levels.
Clock select input. When LOW, selects CLK0. When HIGH, selects CLK1.
LVCMOS / LVTTL interface levels.
Single-ended reference clock inputs. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_1 is the input. XTAL_2 is the output.
Analog supply pin.
Inverted clock select for QC2 and QC3 outputs. LVCMOS / LVTTL interface levels.
Power supply ground.
Single-ended Bank C clock outputs. LVCMOS/ LVTTL interface levels.
Output power supply pins.
Select pins for Bank C outputs. LVCMOS / LVTTL interface levels. See Table 3A.
Synchronization output for Bank A and Bank C. Refer to Figure 1, Timing Diagrams.
LVCMOS / LVTTL interface levels.
Power supply pin.
Single-ended feedback clock output. LVCMOS / LVTTL interface levels.
External feedback. LVCMOS / LVTTL interface levels.
Single-ended Bank B clock outputs. LVCMOS/ LVTTL interface levels.
Select pins for Bank B outputs. LVCMOS / LVTTL interface levels. See Table 3A.
Select pins for Bank A outputs. LVCMOS / LVTTL interface levels. See Table 3A.
Single-ended Bank A clock outputs. LVCMOS/ LVTTL interface levels.
Selects VCO. When HIGH, selects VCO ÷ 1. When LOW, selects VCO ÷ 2.
LVCMOS / LVTTL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2015 Integrated Device Technology, Inc
4
December 7, 2015

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87972I-147 전자부품, 판매, 대치품
87972I-147 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, VDD
Inputs, VI
Outputs, VO
Package Thermal Impedance, JA
Storage Temperature, TSTG
Rating
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
42.3C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
VDD
VDDA
VDDO
IDD
IDDA
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.135 3.3 3.465
3.135 3.3 3.465
3.135 3.3 3.465
250
20
Units
V
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions Minimum Typical Maximum
Units
VIH Input High Voltage
VCO_SEL, PLL_SEL,
REF_SEL, CLK_SEL,
EXT_FB, FSEL_FB[0:2],
VIL
Input Low Voltage FSEL_A[0:1], FSEL_B[0:1],
FSEL_C[0:1], FRZ_DATA
2
VDD + 0.3
V
-0.3 0.8 V
CLK0, CLK1,
INV_CLK, FRZ_CLK
-0.3 1.3 V
IIN Input Current
VOH Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1
IOH = -20mA
IOL = 20mA
2.4
±120
0.5
µA
V
V
NOTE 1: Outputs terminated with 50to VDDO/2. See Parameter Measurement Information section. Load Test Circuit diagram.
©2015 Integrated Device Technology, Inc
7
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부품번호상세설명 및 기능제조사
87972I-147

1-to-12 LVCMOS/LVTTL Clock Multiplier/Zero Delay Buffer

IDT
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