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부품번호 | 8L30205 기능 |
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기능 | Crystal or Differential to LVCMOS/LVTTL Clock Buffer | ||
제조업체 | IDT | ||
로고 | |||
전체 20 페이지수
Crystal or Differential to LVCMOS/
LVTTL Clock Buffer
8L30205
DATA SHEET
General Description
The 8L30205 is a low skew, 1-to-5 LVCMOS / LVTTL Fanout Buffer.
The low impedance LVCMOS/LVTTL outputs are designed to drive
50 series or parallel terminated transmission lines.
The 8L30205 is characterized at full 3.3V and 2.5V, mixed 3.3V/2.5V,
3.3V/1.8V, 3.3V/1.5V, 2.5V/1.8V and 2.5V/1.5V output operating
supply modes. The input clock is selected with a differential clock
input or a crystal input. The differential input can be wired to accept
a single-ended input. The internal oscillator circuit is automatically
disabled if the crystal input is not selected.
Features
• Five LVCMOS / LVTTL outputs up to 200MHz
• Differential input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
• Crystal Oscillator Interface
• Crystal input frequency range: 10MHz to 40MHz
• Additive RMS phase jitter: 30fs (typical)
• Synchronous output enable to avoid clock glitch
• Power supply modes:
Core / Output
3.3V / 3.3V
2.5V / 2.5V
3.3V / 2.5V
3.3V / 1.8V
3.3V / 1.5V
2.5V / 1.8V
2.5V / 1.5V
• -40°C to 85°C ambient operating temperature
• Supports case temperature up to 105°C
• Available in lead-free (RoHS 6) package
Block Diagram
Pin Assignment
SEL
Pulldown
CLK
nCLK
Pulldown
Pullup/ Pulldown
0
XTAL_OUT
XTAL_IN
OSC
1
Bank A
Bank B
Q0 24 23 22 21 20 19
GND 1
18 VDDO
Q1
VDDO 2
17 Q4
Q0 3
GND 4
Q2
8L30205
16 GND
15 Q3
Q1 5
Q3
VDDO 6
14 VDDO
13 Q2
Q4 7 8 9 10 11 12
OE Pulldown
SYNC
24-pin, 4mm x 4mm VFQFN Package
8L30205 REVISION 1 11/18/15
1 ©2015 Integrated Device Technology, Inc.
8L30205 DATA SHEET
Function Tables
Table 3A. SEL Function Table
Control Input
SEL Selected Input Clock
0 (default)
CLK, nCLK
1 XTAL
Table 3B. OE Function Table
Control Input
Function
OE Q[0:4]
0 (default)
High-Impedance
1 Enabled
Table 3C. Input/Output Operation Table1
Input State
OE SEL CLK, nCLK
0 X Do Not Care
1 1 Do Not Care
CLK = nCLK = Open
1 0 CLK = HIGH, nCLK = LOW
CLK = LOW, nCLK = HIGH
NOTE 1. The device must have switching edge to obtain output states.
Output State
Q[0:4]
High-Impedance
Active
LOW
HIGH
LOW
CLK /
nCLK
OE
Q[0:4]
High Impedance
tDIS
Figure 1. OE Timing Diagram
NOTE: The outputs will enable or disable 2 to 3 clock cycles after the transition on the OE input.
tEN
CRYSTAL OR DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK BUFFER
4
REVISION 1 11/18/15
4페이지 8L30205 DATA SHEET
Table 4D. Differential DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
IIH Input High Current
CLK, nCLK VDD = VIN = 3.465V or 2.625V
IIL
VPP
VCMR
Input Low Current
CLK
nCLK
Peak-to-Peak Input Voltage1
Common Mode Input Voltage1, 2
VDD = 3.465V or 2.625V,
VIN = 0V
VDD = 3.465V or 2.625V,
VIN = 0V
NOTE 1. VIL should not be less than -0.3V.
NOTE 2. Common mode voltage is defined at the crosspoint.
-5
-150
0.15
0.5
Maximum
150
1.5
VDD – 0.85
Units
µA
µA
µA
V
V
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Load Capacitance
Test Conditions
Minimum Typical Maximum
Fundamental
10 40
50
7
12 18
Units
MHz
pF
pF
REVISION 1 11/18/15
7 CRYSTAL OR DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK BUFFER
7페이지 | |||
구 성 | 총 20 페이지수 | ||
다운로드 | [ 8L30205.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
8L30205 | Crystal or Differential to LVCMOS/LVTTL Clock Buffer | IDT |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |