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8T39S06A PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8T39S06A
기능 Crystal or Differential to Differential Clock Fanout Buffer
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8T39S06A 데이터시트, 핀배열, 회로
Crystal or Differential to
Differential Clock Fanout Buffer
8T39S06A
Datasheet
General Description
The 8T39S06A is a high-performance clock fanout buffer. The input
clock can be selected from two differential inputs or one crystal input.
The internal oscillator circuit is automatically disabled if the crystal
input is not selected. The crystal pin can be driven by a single-ended
clock.The selected signal is distributed to six differential outputs
which can be configured as LVPECL, LVDS or HCSL outputs. In
addition, an LVCMOS output is provided. All outputs can be disabled
into an high-impedance state. The device is designed for a signal
fanout of high-frequency, low phase-noise clock and data signal. The
outputs are at a defined level when inputs are open or tied to ground.
It is designed to operate from a 3.3V or 2.5V core power supply, and
either a 3.3V or 2.5V output operating supply.
Features
Two differential reference clock input pairs
Differential input pairs can accept the following input
levels: LVPECL, LVDS, HCSL, HSTL and Single-ended
Crystal Oscillator Interface
Crystal input frequency range: 10MHz to 40MHz
Maximum Output Frequency
LVPECL - 2GHz
LVDS - 2GHz
HCSL - 250MHz
LVCMOS - 250MHz
Two banks, each has three differential output pairs that can be
configured as LVPECL or LVDS or HCSL
One single-ended reference output with synchronous enable to
avoid clock glitch
Output skew: 80ps (maximum)
(Bank A and Bank B at the same output level)
Part-to-part skew: 200ps (typical)
Additive RMS phase jitter @ 156.25MHz, (12kHz - 20MHz):
34.7fs (typical), 3.3V/ 3.3V
Supply voltage modes:
VDD/VDDO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
©2016 Integrated Device Technology, Inc.
1
May 20, 2016




8T39S06A pdf, 반도체, 판매, 대치품
8T39S06A Datasheet
Pin Description and Pin Characteristic Tables
Table 1: Pin Descriptions
Number
Name
Type
1
GND
Power
2
VDDOA
Power
3
QA0
Output
4
nQA0
Output
5
VDDOA
Power
6
QA1
Output
7
nQA1
Output
8
QA2
Output
9
nQA2
Output
10
SMODEA0
Input
Pulldown
11
VDD
Power
12
XTAL_IN
Input
13 XTAL_OUT Output
14
REF_SEL0
Input
Pulldown
15
CLK0
Input
Pullup/
Pulldown
16
nCLK0
Input
Pullup/
Pulldown
17
REF_SEL1
Input
Pulldown
18
SMODEB0
Input
Pulldown
19
GND
Power
20
nQB2
Output
21
QB2
Output
22
nQB1
Output
23
QB1
Output
24
VDDOB
Power
25
nQB0
Output
26
QB0
Output
27
VDDOB
Power
28
GND
Power
29
SMODEB1
Input
Pulldown
30
nCLK1
Input
Pullup/
Pulldown
31
CLK1
Input
Pullup/
Pulldown
32
VDD
Power
Description
Power supply ground.
Output supply pin for Bank QA outputs.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pin for Bank QA outputs.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Output driver select for Bank A outputs. See Table 8 for function.
LVCMOS/LVTTL interface levels.
Power supply pin.
Crystal oscillator interface.
Crystal oscillator interface.
Input clock selection. LVCMOS/LVTTL interface levels.
See Table 3 for function.
Non-inverting differential clock. Internally biased to 0.33VDD.
Inverting differential clock. Internally biased to 0.4VDD.
Input clock selection. LVCMOS/LVTTL interface levels.
See Table 3 for function.
Output driver select for Bank B outputs. See Table 9 for function.
LVCMOS/LVTTL interface levels.
Power supply ground.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pin for Bank QB outputs.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pin for Bank QB outputs.
Power supply ground.
Output driver select for Bank B outputs. See Table 9 for function.
LVCMOS/LVTTL interface levels.
Inverting differential clock. Internally biased to 0.4VDD.
Non-inverting differential clock. Internally biased to 0.33VDD.
Power supply pin.
©2016 Integrated Device Technology, Inc.
4
May 20, 2016

4페이지










8T39S06A 전자부품, 판매, 대치품
Table 6: Input/Output Operation Table, SMODEA
Input Status
SMODEA[1:0]
REF_SEL[1:0]
CLKx and nCLKx
11
Don’t care
Don’t Care
00, 01 or 10
10 or 11
Don’t Care
CLK0 and nCLK0 are both open circuit
00, 01 or 10
00 (default)
CLK0 and nCLK0 are tied to ground
CLK0 is high, nCLK0 is low
CLK0 is low, nCLK0 is high
CLK1 and nCLK1 are both open circuit
00, 01 or 10
01
CLK1 and nCLK1 are tied to ground.
CLK1 is high, nCLK1 is low
CLK1 is low, nCLK1 is high
Table 7: Input/Output Operation Table, SMODEB
Input Status
SMODEB[1:0] REF_SEL[1:0] CLKx and nCLKx
11
Don’t care
Don’t Care
00, 01 or 10
10 or 11
Don’t Care
CLK0 and nCLK0 are both open circuit
00, 01 or 10
00 (default)
CLK0 and nCLK0 are tied to ground
CLK0 is high, nCLK0 is low
CLK0 is low, nCLK0 is high
CLK1 and nCLK1 are both open circuit
00, 01 or 10
01
CLK1 and nCLK1 are tied to ground
CLK1 is high, nCLK1 is low
CLK1 is low, nCLK1 is high
©2016 Integrated Device Technology, Inc.
7
8T39S06A Datasheet
Output State
QA[2:0], nQA[2:0]
High Impedance
Fanout Crystal Oscillator
QA[2:0] = Low
nQA[2:0] = High
QA[2:0] = Low
nQA[2:0] = High
QA[2:0] = High
nQA[2:0] = Low
QA[2:0] = Low
nQA[2:0] = High
QA[2:0] = Low
nQA[2:0] = High
QA[2:0] = Low
nQA[2:0] = High
QA[2:0] = High
nQA[2:0] = Low
QA[2:0] = Low
nQA[2:0] = High
Output State
QB[2:0], nQB[2:0]
High Impedance
Fanout Crystal Oscillator
QB[2:0] = Low
nQB[2:0] = High
QB[2:0] = Low
nQB[2:0] = High
QB[2:0] = High
nQB[2:0] = Low
QB[2:0] = Low
nQB[2:0] = High
QB[2:0] = Low
nQB[2:0] = High
QB[2:0] = Low
nQB[2:0] = High
QB[2:0] = Low
nQB[2:0] = High
QB[2:0] = Low
nQB[2:0] = High
May 20, 2016

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8T39S06A

Crystal or Differential to Differential Clock Fanout Buffer

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