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PDF 8T39S06A Data sheet ( Hoja de datos )
| Número de pieza | 8T39S06A | |
| Descripción | Crystal or Differential to Differential Clock Fanout Buffer | |
| Fabricantes | IDT | |
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Crystal or Differential to
Differential Clock Fanout Buffer
8T39S06A
Datasheet
General Description
The 8T39S06A is a high-performance clock fanout buffer. The input
clock can be selected from two differential inputs or one crystal input.
The internal oscillator circuit is automatically disabled if the crystal
input is not selected. The crystal pin can be driven by a single-ended
clock.The selected signal is distributed to six differential outputs
which can be configured as LVPECL, LVDS or HCSL outputs. In
addition, an LVCMOS output is provided. All outputs can be disabled
into an high-impedance state. The device is designed for a signal
fanout of high-frequency, low phase-noise clock and data signal. The
outputs are at a defined level when inputs are open or tied to ground.
It is designed to operate from a 3.3V or 2.5V core power supply, and
either a 3.3V or 2.5V output operating supply.
Features
• Two differential reference clock input pairs
• Differential input pairs can accept the following input
levels: LVPECL, LVDS, HCSL, HSTL and Single-ended
• Crystal Oscillator Interface
• Crystal input frequency range: 10MHz to 40MHz
• Maximum Output Frequency
LVPECL - 2GHz
LVDS - 2GHz
HCSL - 250MHz
LVCMOS - 250MHz
• Two banks, each has three differential output pairs that can be
configured as LVPECL or LVDS or HCSL
• One single-ended reference output with synchronous enable to
avoid clock glitch
• Output skew: 80ps (maximum)
(Bank A and Bank B at the same output level)
• Part-to-part skew: 200ps (typical)
• Additive RMS phase jitter @ 156.25MHz, (12kHz - 20MHz):
34.7fs (typical), 3.3V/ 3.3V
• Supply voltage modes:
VDD/VDDO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
©2016 Integrated Device Technology, Inc.
1
May 20, 2016
1 page  
8T39S06A Datasheet
Number
Name
Type
Description
33
REFOUT
Output
Single-ended reference clock output. LVCMOS/LVTTL interface levels.
34
VDDOREF
Power
Output supply pin for REFOUT output.
35
OE_SE
Input
Pulldown Output enable. LVCMOS/LVTTL interface levels. See Table 4.
36
SMODEA1
Input
Pulldown
Output driver select for Bank A outputs. See Table 8 for function.
LVCMOS/LVTTL interface levels.
0
ePAD
Power
Connect ePAD to ground to ensure proper heat dissipation.
NOTE: Pulldown and Pullup refer to an internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2: Pin Characteristics
Symbol
Parameter
CIN
Input
Capacitance
OE_SE,
SMODEx[1:0],
REF_SEL[1:0]
RPULLDOWN
RPULLUP
Input Pulldown Resistor
Input Pullup CLK0, CLK1
Resistor
nCLK0, nCLK1
Power
CPD Dissipation REFOUT
Capacitance
ROUT
Output
Impedance
REFOUT
Test Conditions
VDDOREF = 3.465V
VDDOREF = 2.625V
VDDOREF = 3.3V
VDDOREF = 2.5V
Minimum
Typical
2
50
100
75
5.3
6.3
52
63
Maximum
Units
pF
k
k
k
pF
pF
©2016 Integrated Device Technology, Inc.
5
May 20, 2016
5 Page 
8T39S06A Datasheet
Table 13: LVCMOS/LVTTL DC Characteristics,
VDD = 3.3V±5%, 2.5V±5%, VDDOREF = 3.3V±5% or 2.5V±5%, GND = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
OE_SE,
VIH
Input
High Voltage
SMODEA[1:0],
SMODEB[1:0],
REF_SEL[1:0]
VDD = 3.3V±5%
VDD = 2.5V±5%
2
1.7
OE_SE,
VIL
Input
Low Voltage
SMODEA[1:0],
SMODEB[1:0],
REF_SEL[1:0]
VDD = 3.3V±5%
VDD = 2.5V±5%
-0.3
-0.3
OE_SE,
IIH
Input
High Current
SMODEA[1:0],
SMODEB[1:0],
VDD = VIN = 3.465V or 2.625V
REF_SEL[1:0]
OE_SE,
IIL
Input
Low Current
SMODEA[1:0],
SMODEB[1:0],
VDD = 3.465V or 2.625V, VIN = 0V
-5
REF_SEL[1:0]
VOH
Output
High Voltage
REFOUT
VOL
Output
Low Voltage
REFOUT
VDDOREF= 3.3V±5%: IOH = -1mA
VDDOREF = 2.5V±5%: IOH = -1mA
VDDOREF = 3.3V±5% or 2.5V±5%:
IOL = 1mA
2.6
1.8
Maximum
VDD + 0.3
VDD + 0.3
0.8
0.7
150
0.5
Units
V
V
V
V
µA
µA
V
V
V
Table 14: Differential DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, GND = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
IIH
Input
High Current
CLK[1:0],
nCLK[1:0]
VDD = VIN = 3.465V or 2.625V
150
IIL
VPP
VCMR
Input
Low Current
CLK[1:0],
nCLK[1:0]
Peak-to-Peak Input Voltage1
Common Mode Input Voltage2
VDD = 3.465V or 2.625V,
VIN = 0V
NOTE 1.Input voltage should not be less than -0.3V and greater than VDD.
NOTE 2.Common mode voltage is defined as the crosspoint.
-150
0.240
GND + 0.5
1.3
VDD – 0.85
Units
µA
µA
V
V
Table 15: LVPECL DC Characteristics, VDDOA = VDDOB = 3.3V±5%, GND = 0V, TA = -40°C to 85°C1
Symbol Parameter
Test Conditions
Minimum Typical
VOH Output High Voltage2
VOL Output Low Voltage2
VDDOX – 1.4
VDDOX – 2.0
VSWING
Peak-to-Peak Output
Voltage Swing
0.6
Maximum
VDDOX – 0.8
VDDOX – 1.6
1.0
NOTE 1.VDDOX denotes VDDOA and VDDOB.
NOTE 2.Outputs terminated with 50to VDDOX – 2V.
Units
V
V
V
©2016 Integrated Device Technology, Inc.
11
May 20, 2016
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 8T39S06A.PDF ] | |
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