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8T39S08A PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8T39S08A
기능 Crystal or Differential to Differential Clock Fanout Buffer
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8T39S08A 데이터시트, 핀배열, 회로
Crystal or Differential-to-Differential
Clock Fanout Buffer
8T39S08A
Datasheet
General Description
The 8T39S08A is a high-performance clock fanout buffer. The input
clock can be selected from two differential inputs or one crystal input.
The internal oscillator circuit is automatically disabled if the crystal
input is not selected. The crystal pin can be driven by a single-ended
clock. The selected signal is distributed to eight differential outputs
which can be configured as LVPECL, LVDS and HCSL outputs. In
addition, an LVCMOS output is provided. All outputs can be disabled
into a high-impedance state. The device is designed for a signal
fanout of high-frequency, low phase-noise clock and data signal. The
outputs are at a defined level when inputs are open or tied to ground.
It is designed to operate from a 3.3V or 2.5V core power supply, and
either a 3.3V or 2.5V output operating supply.
Features
Two differential reference clock input pairs
Differential input pairs can accept the following input levels:
LVPECL, LVDS, HCSL, HSTL and Single-ended
Crystal Oscillator Interface
Crystal input frequency range: 10MHz to 40MHz
Maximum Output Frequency
LVPECL - 2GHz
LVDS - 2GHz
HCSL - 250MHz
LVCMOS - 250MHz
Two banks, each has four differential output pairs that can be
configured as LVPECL or LVDS or HCSL
One single-ended reference output with synchronous enable to
avoid clock glitch
Output skew: 80ps (maximum)
(Bank A and Bank B at the same output level)
Part-to-part skew: 200ps (typical)
Additive RMS phase jitter@ 156.25MHz, (12kHz - 20MHz):
34.7fs (typical), 3.3V/ 3.3V
Supply voltage modes:
VDD/VDDO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
©2016 Integrated Device Technology, Inc.
1
May 19, 2016




8T39S08A pdf, 반도체, 판매, 대치품
8T39S08A Datasheet
Number
34
35
36
37
38
39
40
0
Name
CLK1
VDD
REFOUT
VDDOREF
OE_SE
SMODEA1
GND
ePAD
Type
Input
Pullup/
Pulldown
Power
Output
Power
Input Pulldown
Input Pulldown
Power
Power
Description
Non-inverting differential clock. Internally biased to 0.33VDD.
Power supply pin.
Single-ended reference clock output. LVCMOS/LVTTL interface levels.
Output supply pin for REFOUT output.
Output enable. LVCMOS/LVTTL interface levels. See Table 3B.
Output driver select for Bank A outputs. See Table 3F for function.
LVCMOS/LVTTL interface levels.
Power supply ground.
Connect ePAD to ground to ensure proper heat dissipation.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Input
Capacitance
OE_SE,
SMODEx[1:0],
REF_SEL[1:0]
RPULLDOWN
RPULLUP
CPD
Input Pulldown Resistor
Input Pullup CLK0, CLK1
Resistor
nCLK0, nCLK1
Power
REFOUT
Dissipation
Capacitance REFOUT
ROUT
Output
Impedance
REFOUT
REFOUT
Test Conditions
VDDOREF = 3.465V
VDDOREF = 2.625V
VDDOREF = 3.3V
VDDOREF = 2.5V
Minimum
Typical
2
50
100
75
5.3
6.3
52
63
Maximum
Units
pF
k
k
k
pF
pF
©2016 Integrated Device Technology, Inc.
4
May 19, 2016

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8T39S08A 전자부품, 판매, 대치품
Table 3F. Output Level Selection Table, QA[3:0], nQA[3:0]
SMODEA1
SMODEA0
Output Type
0 0 LVPECL (default)
0 1 LVDS
1 0 HCSL
1 1 High-Impedance
Table 3G. Output Level Selection Table, QB[3:0], nQB[3:0]
SMODEB1
SMODEB0
Output Type
0 0 LVPECL (default)
0 1 LVDS
1 0 HCSL
1 1 High-Impedance
8T39S08A Datasheet
©2016 Integrated Device Technology, Inc.
7
May 19, 2016

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부품번호상세설명 및 기능제조사
8T39S08A

Crystal or Differential to Differential Clock Fanout Buffer

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