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8T39S11A PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8T39S11A
기능 Crystal or Differential to Differential Clock Fanout Buffer
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8T39S11A 데이터시트, 핀배열, 회로
Crystal or Differential-to-Differential
Clock Fanout Buffer
8T39S11A
Datasheet
General Description
The 8T39S11A is a high-performance clock fanout buffer. The input
clock can be selected from two differential inputs or one crystal input.
The internal oscillator circuit is automatically disabled if the crystal
input is not selected. The crystal pin can be driven by a single-ended
clock.The selected signal is distributed to ten differential outputs
which can be configured as LVPECL, LVDS or HSCL outputs. In
addition, an LVCMOS output is provided. All outputs can be disabled
into a high-impedance state. The device is designed for a signal
fanout of high-frequency, low phase-noise clock and data signal. The
outputs are at a defined level when inputs are open or tied to ground.
It is designed to operate from a 3.3V or 2.5V core power supply, and
either a 3.3V or 2.5V output operating supply.
Features
Two differential reference clock input pairs
Differential input pairs can accept the following differential input
levels: LVPECL, LVDS, HCSL, HSTL or Single Ended
Crystal Input accepts 10MHz to 40MHz Crystal or Single Ended
Clock
Maximum Output Frequency
LVPECL - 2GHz
LVDS - 2GHz
HCSL - 250MHz
LVCMOS - 250MHz
Two banks, each has five differential output pairs that can be
configured as LVPECL or LVDS or HCSL
One single-ended reference output with synchronous enable to
avoid clock glitch
Output skew: 80ps (maximum)
(Bank A and Bank B at the same output level)
Part-to-part skew: 200ps (typical)
Additive RMS phase jitter @ 156.25MHz:
5.6fs RMS (10kHz - 1 MHz), typical @ 3.3V/ 3.3V
34.7fs RMS (12kHz - 20MHz), typical @ 3.3V/ 3.3V
Supply voltage modes:
VDD/VDDO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
©2015 Integrated Device Technology, Inc.
1
December 17, 2015




8T39S11A pdf, 반도체, 판매, 대치품
8T39S11A Datasheet
Table 1: Pin Descriptions1 (Continued)
Number
Name
Type
Description
33
nQB1
Output
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
34 QB1 Output
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
35
nQB0
Output
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
36 QB0 Output
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
37
GND
Power
Power supply ground.
38 nc Unused
No connect pin.
39
SMODEB1
Input
Pulldown
Output driver select for Bank B outputs. See Table 9 for function.
LVCMOS/LVTTL interface levels.
40
nCLK1
Input
Pullup/
Pulldown
Inverting differential clock. Internally biased to 0.4VDD.
41
CLK1
Input
Pullup/
Pulldown
Non-inverting differential clock. Internally biased to 0.33VDD.
42 VDD Power
43
GND
Power
Power supply pin.
Power supply ground.
44
REFOUT
Output
Single-ended reference clock output. LVCMOS/LVTTL interface levels.
45
VDDOREF
Power
Output supply pin for REFOUT output.
46
OE_SE
Input
Pulldown Output enable. LVCMOS/LVTTL interface levels. See Table 4.
47
SMODEA1
Input
Pulldown
Output driver select for Bank A outputs. See Table 8 for function.
LVCMOS/LVTTL interface levels.
48
GND
Power
Power supply ground.
ePad
GND_EP
Power
Connect ePad to ground to ensure proper heat dissipation.
NOTE 1. Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2: Pin Characteristics
Symbol
Parameter
CIN
Input
Capacitance
OE_SE,
SMODEx[1:0],
REF_SEL[1:0]
RPULLDOWN
RPULLUP
Input Pulldown Resistor
Input Pullup CLK0, CLK1
Resistor
nCLK0, nCLK1
Power
REFOUT
CPD
Dissipation
Capacitance REFOUT
ROUT
Output
Impedance
REFOUT
REFOUT
Test Conditions
VDDOREF = 3.465V
VDDOREF = 2.625V
VDDOREF = 3.3V
VDDOREF = 2.5V
Minimum
Typical
2
50
100
75
5.3
6.3
52
63
Maximum
Units
pF
k
k
k
pF
pF
©2015 Integrated Device Technology, Inc.
4
December 17, 2015

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8T39S11A 전자부품, 판매, 대치품
8T39S11A Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, VDD
Inputs, VI
XTAL_IN
Other Inputs
Outputs, VO, (HCSL, LVCMOS)
Outputs, IO, (LVPECL)
Continuous Current
Surge Current
Outputs, IO, (LVDS)
Continuous Current
Surge Current
Junction Temperature
Storage Temperature, TSTG
NOTE 1. VDDOX denotes VDDOA, VDDOB and VDDOREF.
Rating
4.6V
0V to 2V
-0.5V to VDD + 0.5V
-0.5V to VDDOX1 + 0.5V
50mA
100mA
10mA
15mA
125°C
-65°C to 150°C
DC Electrical Characteristics
Table 10: Power Supply DC Characteristics, VDD = VDDOA = VDDOB = VDDOREF = 3.3V±5%, GND = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
VDD Power Supply Voltage
3.135
3.3
3.465
V
VDDOA,
VDDOB, VDDOREF
Output Supply Voltage
3.135
3.3
3.465
V
IDD
IDDOA + IDDOB
Power Supply Current
Output Supply Current1
SMODEA/B[1:0] = 01
SMODEA/B[1:0] = 01
101 114 mA
215 242 mA
IEE
Power Supply Current
SMODEA/B[1:0] = 00 (default)
168 195 mA
IDD
IDDOA + IDDOB
Power Supply Current
Output Supply Current2
SMODEA/B[1:0] = 10
SMODEA/B[1:0] = 10
93 106 mA
81 93 mA
NOTE 1. Differential outputs are terminated with 100.
NOTE 2. Differential outputs are running at 250MHz and floating.
©2015 Integrated Device Technology, Inc.
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December 17, 2015

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8T39S11A

Crystal or Differential to Differential Clock Fanout Buffer

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