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부품번호 8V97051 기능
기능 Low Power Wideband Fractional RF Synthesizer / PLL
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8V97051 데이터시트, 핀배열, 회로
Low Power Wideband Fractional
RF Synthesizer / PLL
8V97051
Datasheet
General Description
The 8V97051 is a high performance Wideband RF Synthesizer / PLL
optimized for use as the local oscillator (LO) in Multi-Carrier,
Multi-mode FDD & TDD Base Station radio card. It is offered in a
compact 5x5, 32-VFQFN package.
The 8V97051 Wideband RF Synthesizer / PLL offers a default
Fractional Mode with the option to use it with an Integer mode. It
requires an external loop filter.
The 8V97051 with integrated Voltage Controlled Oscillator (VCO)
supports output frequencies from 34.375MHz to 4400MHz and
maintains superior phase noise and spurious performance.
RF_OUT[A:B] output drivers have independently programmable
output power ranging from –4dBm to +7dBm. The RF_OUT outputs
can be muted. The mute function is accessible via a SPI command
or mute pin.
The operation of the 8V97051 is controlled by writing to registers
through a 3-wire SPI interface. The 8V97051 also has an additional
option that allows users to read back values from registers by
configuring the MUX_OUT pin as a SDO for the SPI interface. The
SPI interface is compatible with 1.8V logic and tolerant to 3.3V.
In multi-service base stations, very low noise oscillators are required
to generate a large variety of frequencies to the mixers while
maintaining excellent phase noise performance and low power. The
8V97051 offers a large tuning range capable of providing multi-band
local oscillator (LO) frequency synthesis in multi-mode base stations,
thus limiting the use of multiple narrow band RF Synthesizers and
reducing the BOM complexity and cost. The device can operate over
-40°C to +85°C industrial temperature range.
Features
• Dual Differential Outputs
• Output frequency range: 34.375MHz to 4400MHz (continuous
range)
• RF Output Divide by 1, 2, 4, 8, 16, 32, 64
• Open Drain Outputs (see Output Distribution Section)
• Fractional-N synthesizer (also supports Integer-N mode)
• 16-bit integer and 12-bit fractional
(16-bit fractional when using the extended registers)
• 3- or 4-wire SPI interface (compatible with 3.3V and 1.8V)
• Single 3.3V supply
• Logic compatibility: 1.8V
• Programmable output power level: -4dBm to +5dBm
(up to +7 when using the extended registers)
• Mute Function
• Ultra low PN for 1.1GHz LO: -143dBc/Hz @ 1MHz Offset, (typical)
• Lock Detect Indicators
• Input Reference frequency: 5MHz to 310MHz
• Power Consumption: 380mW (typical) (RF_OUTB disabled)
• 32-Lead, 5x5 VFQFN package
• Automatic VCO band selection (Autocal feature)
• -40°C to +85°C ambient operating temperature
Supports case temperature 105°C operations
• Lead-free (RoHS 6) packaging
Applications
• Wireless Infrastructure
• Test Equipment
• CATV Equipment
• Military and Aerospace
• Wireless LAN
• Clock Generation
©2016 Integrated Device Technology, Inc.
1
Revision 4, September 22, 2016




8V97051 pdf, 반도체, 판매, 대치품
8V97051 Datasheet
Table 9G. Register 4: 1-Bit RF_OUTB Select. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 9H. Register 4: 1-Bit RF_OUTB Enable. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 9I. Register 4: 2-Bit RF_OUTB Output Power. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 9J. Register 4: 1-Bit RF_OUTA Enable. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 9K. Register 4: 2-Bit RF_OUTA Output Power. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 9L. Register 4: 3-Bit Control Bits. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 10A. Register 5 Bit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 10B. Register 5: 2-Bit LD (Lock Detect) Pin Mode. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 10C. Register 5: 3-Bit Control Bits. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Extended Registers, (Registers 6 and 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 11A. Register 6 Bit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 11B. Register 6: 1-Bit Digital Lock Detect. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 11C. Register 6: 1-Bit Band Select Status (Read Only). Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 11D. Register 6: 2-Bit Extra Lock Detect Precision. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 11E. Register 6: 1-Bit Extra Bit of RF_OUTB Power. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 11F. Register 6: 1-Bit Extra Bit of RF_OUTA Power. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 11G. Register 6: 2-Bit Sigma Delta Modulator Order Configuration. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 11H. Register 6: 2-Bit Dither Gain Configuration. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 11I. Register 6: 1-Bit Dither Noise Shaping Configuration. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 11J. Register 6: 1-Bit Sigma Delta Modulator Type Configuration. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 11K. Register 6: 2-Bit VCO Band Selection Accuracy Configuration. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 11L. Register 6: 4-Bit Extra Most Significant Bits of Band Select Divider. Function Description . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 11M. Register 6: 3-Bit Control Bits. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 12A. Register 7 Bit Allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 12B. Register 7: 1-Bit Loss of Digital Lock. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 12C. Register 7: 1-Bit Loss of Analog Lock. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 12D. Register 7: 1-Bit SPI Error. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 12E. Register 7: 3-Bit Revision ID. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 12F. Register 7: 4-Bit Device ID. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 12G. Register 7: 1-Bit Resolution Select. Function Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 12H. Register 7: 4-Bit Extra Bits of PHASE Value. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 12I. Register 7: 4-Bit Extra Bits of MOD Value. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 12J. Register 7: 4-Bit Extra Bits of FRAC Value. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 12K. Register 7: 1-Bit SCLKE. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 12L. Register 7: 1-Bit READBACK_ADDR. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 12M. Register 7: 1-Bit SPI_R_WN. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 12N. Register 7: 3-Bit Control Bits. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 13. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 14A. Power Supply DC Characteristics, VDDX = VDDA = 3.3V ± 5%, TA = -40°C to +85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 14B. Output Divider Incremental Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 14C. Typical Current by Power Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 14D. LVCMOS DC Characteristics, VDDX = VDDA = 3.3V ± 5%, TA = -40°C to 85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
©2016 Integrated Device Technology, Inc.
4
Revision 4, September 22, 2016

4페이지










8V97051 전자부품, 판매, 대치품
8V97051 Datasheet
Pin Description and Characteristic Tables
Table 1. Pin Description1
Pin Name
Type
Description
1 SCLK LVCMOS Input Pulldown Serial Clock Input. High-Impedance CMOS input. 1.8V logic. 3.3V tolerant.
2 SDI
LVCMOS Input
Pullup Serial Data Input. High-Impedance CMOS input. 1.8V logic. 3.3V tolerant.
3 nCS
LVCMOS Input
Load Enable. High-Impedance CMOS input. 1.8V logic. 3.3V tolerant. Active
Pulldown Low.
4 CE
LVCMOS Input
Pullup
Chip Enable. On logic Low, powers down the device and puts the charge
pump into High-Impedance mode. Powers up the device on logic High.
5 FLSW
Analog
Fast Lock Switch. A connection should be made from the loop filter to this pin
when using the fast lock mode.
6 V_CP
Power
Charge Pump Power Supply. V_CP must have the same value as VDDA. Place
decoupling capacitors to the ground plane as close to this pin as possible.
7 CP_OUT
Analog
Charge Pump Output. When enabled, this output provides ±ICP to the
external loop filter. The output of the loop filter is connected to VTUNE to drive
the internal VCO.
8 GND_CP
Ground
Charge Pump Power Supply Ground.
9 GNDA
Ground
Analog Power Supply Ground.
10 VDDA
Power
11
GNDA_VCO
Ground
Analog Supply. This pin ranges from 3.3V ± 5%. VDDA must have the same
value as VDDD.
VCO Analog Power Supply Ground.
12 RF_OUTA
Output
13 nRF_OUTA Output
14 RF_OUTB
Output
15 nRF_OUTB Output
16 VVCO
Power
17 VVCO
Power
18
GNDA_VCO
Ground
Clock Output pair A. The output level is programmable.
Clock Output pair A. The output level is programmable.
Clock Output pair B. The output level is programmable.
Clock Output pair B. The output level is programmable.
VCO Supply. This pin ranges from 3.3V ± 5%. VVCO must have the same
value as VDDA.
VCO Supply. This pin ranges from 3.3V ± 5%. VVCO must have the same
value as VDDA.
VCO Analog Power Supply Ground.
19 VBIAS
Analog
Place decoupling capacitors (0.1µF) to ground, as close to this pin as
possible.
20 VTUNE
21
GNDA_VCO
Ground
Control Input to tune the VCO.
VCO Analog Power Supply Ground.
22 RCP
23 VCOM
Analog
Analog
Sets the charge pump current. Requires external resistor.
Place decoupling capacitors (0.1µF) to ground, as close to this pin as
possible.
24 VREF
Analog
Place decoupling capacitors (0.1µF) to ground, as close to this pin as
possible.
25 LD
LVCMOS Output
Lock Detect. Logic High indicates PLL lock. Logic Low indicates loss of PLL
lock.
©2016 Integrated Device Technology, Inc.
7
September 22, 2016

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관련 데이터시트

부품번호상세설명 및 기능제조사
8V97051

Low Power Wideband Fractional RF Synthesizer / PLL

IDT
IDT
8V97053

Low Power Wideband Fractional RF Synthesizer / PLL

IDT
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