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74HC165D PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 74HC165D
기능 8-Bit Shift Register
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74HC165D 데이터시트, 핀배열, 회로
CMOS Digital Integrated Circuits Silicon Monolithic
74HC165D
74HC165D
1. Functional Description
• 8-Bit Shift Register (P-IN, S-OUT)
2. General
The 74HC165D is a high speed CMOS 8-BIT PARALLEL/SERIAL-IN, SERIAL-OUT SHIFT REGISTER
fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power
dissipation.
It consists of parallel-in or serial-in, serial-out 8-bit shift register with a gated clock inputs. When the SHIFT/
LOAD input is held high, the serial data input is enabled and the eight frip-frops perform serial shifting with
each clock pulse.
When the SHIFT/LOAD input is held low, the parallel data is loaded synchronously into the register at positive
going transition of the clock pulse.
The CK-INH input should be shifted high only when the CK input is held high.
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
3. Features
(1) High speed: fMAX = 56 MHz (typ.) at VCC = 5 V
(2) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25
(3) Balanced propagation delays: tPLH tPHL
(4) Wide operating voltage range: VCC(opr) = 2.0 V to 6.0 V
4. Packaging
SOIC16
©2016 Toshiba Corporation
1
Start of commercial production
2016-05
2016-05-26
Rev.2.0




74HC165D pdf, 반도체, 판매, 대치품
10. System Diagram
74HC165D
©2016 Toshiba Corporation
4
2016-05-26
Rev.2.0

4페이지










74HC165D 전자부품, 판매, 대치품
74HC165D
13.3. Timing Requirements (Unless otherwise specified, Ta = 25 , Input: tr = tf = 6 ns)
Characteristics
Minimum pulse width
(CK, CK INH)
Minimum pulse width
(S/L)
Minimum setup time
(PI-S/L)
Minimum setup time
(SI-CK, CK INH)
Minimum setup time
(S/L-CK, CK INH)
Minimum hold time
(PI-S/L)
Minimum hold time
(SI-CK, CK INH)
Minimum hold time
(S/L-CK, CK INH)
Minimum removal time
(CK INH-CK), (CK-CK INH)
Clock frequency
Symbol
tw(L),tw(H)
tw(L)
tS
tS
tS
th
th
th
trem
f
Test Condition
VCC (V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Limit
75
15
13
75
15
13
75
15
13
75
15
13
75
15
13
0
0
0
0
0
0
0
0
0
75
15
13
7
30
41
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
©2016 Toshiba Corporation
7
2016-05-26
Rev.2.0

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