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PDF GAL20V8Z Data sheet ( Hoja de datos )
| Número de pieza | GAL20V8Z | |
| Descripción | Zero Power E2CMOS PLD | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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Features
• ZERO POWER E2CMOS TECHNOLOGY
— 100µA Standby Current
— Input Transition Detection on GAL20V8Z
— Dedicated Power-down Pin on GAL20V8ZD
— Input and Output Latching During Power Down
• HIGH PERFORMANCE E2CMOS TECHNOLOGY
— 12 ns Maximum Propagation Delay
— Fmax = 83.3 MHz
— 8 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Output Drive
— UltraMOS® Advanced CMOS Technology
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Architecturally Similar to Standard GAL20V8
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Battery Powered Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
GAL20V8Z
GAL20V8ZD
Zero Power E2CMOS PLD
Functional Block Diagram
I/CLK
I
I
I/DPP
IMUX
CLK
8 OLMC
8 OLMC
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
I 8 OLMC
OE
I
IMUX
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/OE
Description
The GAL20V8Z and GAL20V8ZD, at 100 µA standby current and
12ns propagation delay provides the highest speed and lowest
power combination PLD available in the market. The
GAL20V8Z/ZD is manufactured using Lattice Semiconductor's ad-
vanced zero power E2CMOS process, which combines CMOS with
Electrically Erasable (E2) floating gate technology.
The GAL20V8Z uses Input Transition Detection (ITD) to put the
device in standby mode and is capable of emulating the full func-
tionality of the standard GAL20V8. The GAL20V8ZD utilizes a
dedicated power-down pin (DPP) to put the device in standby mode.
It has 19 inputs available to the AND array.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
DIP
PLCC
I/CLK
I
I
4 2 28 26
I/DPP 5
2 5 I/O/Q I/D P P
I
I7
NC
I9
GAL20V8Z
GAL20V8ZD
Top View
I/O/Q
2 3 I/O/Q
NC
2 1 I/O/Q
I
I
I
I
I
I/O/Q
I
I 1 1 1 2 1 4 1 6 1 8 1 9 I/O/Q
I
I
GND
1 24 Vcc
2 23 I
3 GAL 22
4 20V8Z 21
5 20V8ZD 20
6 19
I/O/Q
I/O/Q
I/O/Q
I/O/Q
7 18 I/O/Q
8 17 I/O/Q
9 16 I/O/Q
10 15 I/O/Q
11 14 I
12 13 I/OE
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
December 1997
20v8zzd_03
1
1 page  
Specifications GAL20V8Z
GAL20V8ZD
Registered Mode Logic Diagram
DIP (PLCC) Package Pinouts
1(2)
2(3)
2640
0 4 8 12 16 20 24 28 32 36 PTD
0000
3(4)
0280
0320
* 4(5)
0600
0640
5(6)
0920
0960
6(7)
1240
1280
7(9)
1560
1600
8(10)
1880
1920
9(11)
2200
2240
10(12)
11(13)
2520
2703
OLMC
XOR-2560
AC1-2632
OLMC
XOR-2561
AC1-2633
OLMC
XOR-2562
AC1-2634
OLMC
XOR-2563
AC1-2635
OLMC
XOR-2564
AC1-2636
OLMC
XOR-2565
AC1-2637
OLMC
XOR-2566
AC1-2638
OLMC
XOR-2567
AC1-2639
23(27)
22(26)
21(25)
20(24)
19(23)
18(21)
17(20)
16(19)
15(18)
14(17)
OE 13(16)
64-USER ELECTRONIC SIGNATURE FUSES
2568, 2569, ....
.... 2630, 2631
Byte7 Byte6 ....
.... Byte1 Byte0
MSB
LSB
SYN-2704
AC0-2705
* Note: Input not available on GAL20V8ZD
5
5 Page 
Specifications GAL20V8Z
SpecificationGs GALA2L02V08VZ8DZ
AC Switching Characteristics
Over Recommended Operating Conditions
TEST
PARAMETER COND1.
DESCRIPTION
tpd A Input or I/O to Combinational Output
tco A Clock to Output Delay
tcf2 — Clock to Feedback Delay
tsu — Setup Time, Input or Feedback before Clock↑
th — Hold Time, Input or Feedback after Clock↑
A Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
fmax3
A Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with
No Feedback
twh — Clock Pulse Duration, High
twl — Clock Pulse Duration, Low
ten B Input or I/O to Output Enabled
B OE to Output Enabled
tdis C Input or I/O to Output Disabled
C OE to Output Disabled
tas — Last Active Input to Standby
tsa4 — Standby to Active Output
COM
COM
-12 -15
UNITS
MIN. MAX. MIN. MAX.
3 12 3 15 ns
2 8 2 10 ns
—6—7
ns
10 — 15 —
ns
0 — 0 — ns
55 — 40 — MHz
62.5 — 45.5 — MHz
83.3 — 62.5 — MHz
6—8—
6—8—
— 12 — 15
— 12 — 15
— 15 — 15
— 12 — 15
60 140 50 150
6 13 5 15
ns
ns
ns
ns
ns
ns
ns
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.
4) Add tsa to tpd, tsu, ten and tdis when the device is coming out of standby state.
Standby Power Timing Waveforms
POWER
Icc
Isb
INPUT or
I/O FEEDBACK
OE
CLK
OUTPUT
tas
tsa tpd
ten, tdis
* tsu
tco
* Note: Rising clock edges
are allowed during tsa but
outputs are not guaranteed.
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet GAL20V8Z.PDF ] | |
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