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PDF M95M02-A125 Data sheet ( Hoja de datos )
| Número de pieza | M95M02-A125 | |
| Descripción | Automotive 2 Mbit serial SPI bus EEPROM | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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SO8 (MN)
150 mil width
M95M02-A125
Automotive 2 Mbit serial SPI bus EEPROM
Datasheet - production data
Features
• Compatible with the Serial Peripheral Interface
(SPI) bus
• Memory array
– 2 Mbit (256 Kbyte) of EEPROM
– Page size: 256 byte
– Write protection by block: 1/4, 1/2 or whole
memory
– Additional Write lockable Page
(Identification page)
• Extended temperature and voltage ranges
– Up to 125 °C (VCC from 2.5 V to 5.5 V)
• Clock frequency
– 10 MHz for VCC ≥ 4.5 V @ 105°C
– 5 MHz for VCC ≥ 2.5 V @ 125°C
• Schmitt trigger inputs for noise filtering
• Short Write cycle time
– Byte Write within 5 ms
– Page Write within 5 ms
• Write cycle endurance
– 4 million Write cycles at 25 °C
– 1.2 million Write cycles at 85 °C
– 100 k Write cycles at 125 °C
• Data retention
– 100 years at 25 °C
• ESD Protection (Human Body Model)
– 3000 V
• Packages
– RoHS-compliant and halogen-free
(ECOPACK2®)
July 2015
This is information on a product in full production.
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M95M02-A125
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Hold mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Write Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Read Lock Status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 35
SO8N – 8-lead plastic small outline, 150 mils body width,
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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M95M02-A125
Operating features
3.3 Hold mode
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
The Hold mode starts when the Hold (HOLD) signal is driven low and the Serial Clock (C) is
low (as shown in Figure 4). During the Hold mode, the Serial Data output (Q) is high
impedance, and the signals present on Serial Data input (D) and Serial Clock (C) are not
decoded. The Hold mode ends when the Hold (HOLD) signal is driven high and the Serial
Clock (C) is or becomes low.
Figure 4. Hold mode activation
#
(/,$
(OLD
CONDITION
(OLD
#COONNDDIITTIIOONN
-36
Deselecting the device while it is in Hold mode resets the paused communication.
3.4
3.4.1
Protocol control and data protection
Protocol control
The Chip Select (S) input offers a built-in safety feature, as the S input is edge-sensitive as
well as level-sensitive: after power-up, the device is not selected until a falling edge has first
been detected on Chip Select (S). This ensures that Chip Select (S) must have been high
prior to going low, in order to start the first operation.
For Write commands (WRITE, WRSR, WRID, LID) to be accepted and executed:
• the Write Enable Latch (WEL) bit must be set by a Write Enable (WREN) instruction
• a falling edge and a low state on Chip Select (S) during the whole command must be
decoded
• instruction, address and input data must be sent as multiple of eight bits
• the command must include at least one data byte
• Chip Select (S) must be driven high exactly after a data byte boundary
Write command can be discarded at any time by a rising edge on Chip Select (S) outside of
a byte boundary.
To execute Read commands (READ, RDSR, RDID, RDLS), the device must decode:
• a falling edge and a low level on Chip Select (S) during the whole command
• instruction and address as multiples of eight bits (byte)
From this step, data bits are shifted out until the rising edge on Chip Select (S).
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