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PDF 8V44S269 Data sheet ( Hoja de datos )
| Número de pieza | 8V44S269 | |
| Descripción | 10-Output Clock Synthesizer | |
| Fabricantes | IDT | |
| Logotipo |  |
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FemtoClock® Crystal-to-LVDS, LVCMOS
10-Output Clock Synthesizer
8V44S269
Datasheet
General Description
The 8V44S269 is a ten LVDS/LVTTL output clock synthesizer
designed for instrumentation and wireless applications. The device
generates four copies of a 125MHz, two copies of a 100MHz
differential LVDS clock and one 50MHz (LVCMOS) signal with
excellent phase jitter performance. The PLL is optimized for a
reference frequency of 25MHz. Both a crystal interface and a
single-ended input are supported for the reference frequency. Three
LVCMOS outputs duplicate the reference frequency and are
provided for clock tree cascade purpose. Each of the four LVCMOS
outputs can be supplied with either 3.3V, 2.5V or 1.8V, forming the
respective LVCMOS output levels of 3.3V, 2.5V or 1.8V. The device
uses IDT’s third generation FemtoClock® technology for an optimum
of high clock frequency and low phase noise performance, combined
with a low power consumption. The device supports a 3.3V voltage
supply and is packaged in a small, lead-free (RoHS 6) 48-lead
VFQFN package.
Features
• Third generation FemtoClock® technology
• 125MHz, 100MHz and 50MHz output clocks synthesized from a
25MHz reference clock or fundamental mode crystal
• Six differential LVDS clock outputs
• QA[0:3] outputs (125MHz) are LVDS compatible
• QB[0:1] outputs (100MHz) are LVDS compatible
• Four single-ended LVCMOS-compatible reference clock outputs
• QC output (50MHz) is LVCMOS 3.3V, 2.5V or 1.8V compatible
• QREF[0:2] (25MHz) are LVCMOS 3.3V, 2.5V or 1.8V compatible
• Crystal interface designed for 25MHz XTAL
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(12kHz - 20MHz): 0.57 (typical)
• RMS phase jitter @ 100MHz, using a 25MHz crystal
(12kHz - 20MHz): 0.58 (typical)
• LVCMOS interface levels for the control input
• I/O supply voltages for LVDS:
Core/Output
3.3V/2.5V
• I/O supply voltages for LVCMOS:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
• Lead-free (RoHS 6) 48-lead VFQFN packaging
• -55°C to 105°C ambient operating temperature
©2016 Integrated Device Technology, Inc.
1
May 9, 2016
1 page  
8V44S269 Datasheet
Table 1. Pin Descriptions1
Number
Name
Type
Description
42
nOEA1
Input
Pull-down Output enable inputs for the QA1 output. See Table 3C on page 6 for
function. LVCMOS/LVTTL interface levels.
43
nOEA0
Input
Pull-down Output enable inputs for the QA0 output. See Table 3C on page 6 for
function. LVCMOS/LVTTL interface levels.
44
REF_SEL
Input
Pull-down Reference select. See Table 3A on page 6 for function.
LVCMOS/LVTTL interface levels.
45
BYPASS
Input
Pull-down PLL bypass mode select. See Table 3B on page 6 for function.
LVCMOS/LVTTL interface levels.
46
GND
Power
47
XTAL_OUT
Crystal
Output
48 XTAL_IN Crystal Input
Ground power supply (0V).
Crystal Output. Crystal oscillator interface.
Crystal Input. Crystal oscillator interface.
— Exposed Pad Ground
Ground power supply (0V). The exposed pad is a ground return path of the
circuit and requires a connection to 0V.
NOTE 1. Pull-down refers to internal input resistors. See Table 2, “Pin Characteristics”.
Table 2. Pin Characteristics1
Symbol
Parameter
Test Conditions
REF_CLK,
nOEA[0:3],
CIN
Input
Capacitance
nOEB[0:1],
nOEC,
nOER[0:1],
REF_SEL,
BYPASS
RPULLDOWN Input Pull-down Resistor
QREF[0:2], QC, VDDOn = 3.3V
ROUT
Output Impedance
QREF[0:2], QC, VDDOn = 2.5V
QREF[0:2], QC, VDDOn = 1.8V
NOTE 1. VDDOn denotes VDDOC, VDDOR0, VDDOR1, VDDOR2.
Minimum Typical Maximum Units
2 pF
51 k
18
23
35
©2016 Integrated Device Technology, Inc.
5
May 9, 2016
5 Page 
Typical Phase Noise at 125MHz, 2.5V (QA Outputs)
8V44S269 Datasheet
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc.
11
May 9, 2016
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet 8V44S269.PDF ] | |
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