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HI-15530 데이터시트 PDF




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부품번호 HI-15530 기능
기능 5V / 3.3V Manchester Encoder / Decoder
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HI-15530 데이터시트, 핀배열, 회로
HI-15530
September 2013
5V / 3.3V Manchester Encoder / Decoder
GENERAL DESCRIPTION
The HI-15530 is a high performance CMOS integrated
circuit designed to meet the requirements of MIL-STD-1553
and similar Manchester II encoded, time division
multiplexed serial data protocols. The HI-15530 contains
both an Encoder and Decoder, which operate
independently.
The HI-15530 is fully compatible with either 5V or 3.3V logic
and transceivers.
The device generates MIL-STD-1553 sync pulses, parity
bits as well as the Manchester II encoding of the data bits.
The decoder recognizes and identifies sync pulses,
decodes data bits, and performs parity checking.
The HI-15530 supports the 1Mbit/s data rate of MIL-STD-
1553 over the full temperature and voltage range.
For applications requiring small footprints and low cost, the
HI-15530 is available in a 24-pin plastic SSOP package.
Ceramic DIP and LCC packages are also available to
achieve the highest level of reliability and to provide drop-in
replacements for obsolete parts from other manufacturers.
FEATURES
! MIL-STD-1553 compatible
! 5V or 3.3V operation
! Interfaces to HI-1567 Transceiver Family
! Small footprint 24-pin plastic SSOP package
option
! Direct replacement for:
Harris/Intersil HD15530
GEC Plessey Semiconductors MAS15530
Aeroflex ACT15530
! 1.25 Mbit/s Maximum Data Rate
! Manchester II Encode and Decode
! Sync identification and Lock-in
! High Temperature -55oC to +200oC option
APPLICATIONS
! MIL-STD-1553 Interfaces
! Smart Munitions
! Stores Management
! Sensor Interfaces
! Instrumentation
PIN CONFIGURATION (Top View)
VALID WORD 1
ENCODER SHIFT CLK 2
TAKE DATA 3
SERIAL DATA OUT 4
DECODER CLK 5
BIPOLAR ZERO IN 6
BIPOLAR ONE IN 7
UNIPOLAR DATA IN 8
DECODER SHIFT CLK 9
COMMAND / DATA SYNC 10
DECODER RESET 11
GND 12
HI-15530PSI
HI-15530PST
HI-15530PSM
24 VDD
23 ENCODER CLK
22 SEND CLK IN
21 SEND DATA
20 SYNC SELECT
19 ENCODER ENABLE
18 SERIAL DATA IN
17 BIPOLAR ONE OUT
16 OUTPUT INHIBIT
15 BIPOLAR ZERO OUT
14 ¸ 6 OUT
13 MASTER RESET
24 Pin SSOP package
(Additional package pin configurations shown inside data sheet)
(DS15530 Rev. K)
HOLT INTEGRATED CIRCUITS
www.holtic.com
09/13




HI-15530 pdf, 반도체, 판매, 대치품
HI-15530
DECODER OPERATION
The Decoder requires a single clock with a frequency of 12
times the desired data rate applied at the DECODER
CLOCK input. The Manchester II coded data can be
presented to the Decoder in one of two ways. The
BIPOLAR ONE and BIPOLAR ZERO inputs will accept
data from a comparator sensed transformer coupled bus as
specified in MIL-STD-1553. The UNIPOLAR DATA input
can only accept non-inverted Manchester II coded data
(e.g. from BIPOLAR ZERO OUT of an Encoder). The
Decoder is free running and continuously monitors its data
input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a valid
sync is recognized (1), the type of sync is indicated on
COMMAND/DATA SYNC output. If the sync character was
a command sync, this output will go high (2) and remain
high for sixteen DECODER SHIFT CLOCK periods (3),
otherwise it will remain low. The TAKE DATA output will go
high and remain high (2) - (3) while the Decoder is
transmitting the decoded data through SERIAL DATA OUT.
The decoded data available at SERIAL DATA OUT is in an
NRZ format. The DECODER SHIFT CLOCK is provided so
that the decoded bits can be shifted into an external register
on every low-to-high transition of this clock (2) - (3). After all
sixteen decoded bits have been transmitted (3) the data is
checked for odd parity. A high on VALID WORD output (4)
indicates a successful reception of a word without any
Manchester or parity errors. At this time the Decoder is
looking for a new sync character to start another output
sequence. VALID WORD will go low approximately 20
DECODER SHIFT CLOCK periods after it goes high if not
reset low sooner by a valid sync and two valid Manchester
bits as shown (1). At any time in the above sequence, a
high input on DECODER RESET during a low-to-high
transition of DECODER SHIFT CLOCK will abort
transmission and initialize the Decoder to start looking for a
new sync character.
UNIPOLAR
DATA IN
BIPOLAR
ONE IN
BIPOLAR
ZERO IN
DECODER
CLK
MASTER
RESET
TRANSITION
FINDER
TAKE DATA
CHARACTER
IDENTIFIER
COMMAND/DATA
SYNC
SERIAL DATA
OUT
SYNCHRONIZER
BIT
RATE
CLK
PARITY
CHECK
VALID
WORD
DECODER
SHIFT CLK
DECODER
RESET
BIT
COUNTER
FIGURE 3. DECODER
TIMING
DECODER
SHIFT CLK
BIPOLAR
ONE IN
BIPLOAR
ZERO IN
TAKE DATA
COMMAND /
DATA SYNC
SERIAL
DATA OUT
VALID WORD
012345678
16 17 18 19
SYNC SYNC 15 14 13 12 11 10
SYNC SYNC 15 14 13 12 11 10
2 10P
2 10P
UNDEFINED
15 14 13 12
4 3 2 10
May be high from previous reception
(1)(2)
FIGURE 4. DECODER OPERATION
(3) (4)
HOLT INTEGRATED CIRCUITS
4

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HI-15530 전자부품, 판매, 대치품
HI-15530
ABSOLUTE MAXIMUM RATINGS
Supply Voltage VDD
-0.3V to +7V
Voltage at any pin
Operating Temperature Range:
Industrial
Extended
Hi-Temp
-0.3V to Vcc +0.3V
-40°C to +85°C
-55°C to +125°C
-55°C to +200°C
Power Dissipation at 25°C
Plastic SSOP
Ceramic DIP
DC Current Drain per pin
Storage Temperature Range:
1.5 W, derate10mW/°C
1.0 W, derate 7mW/°C
±10mA
-65°C to +150°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VDD = 3.0 V to 5.5 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
CONDITIONS
LIMITS
UNIT
MIN
TYP
MAX
Input Voltage
Input Voltage HI
Input Voltage LO
VIH
VIL
70% VDD
V
30% VDD V
Clock Input Voltage
Input Voltage HI
Input Voltage LO
VIHC
VILC
VDD-0.5
0.5V
V
V
Input Leakage Current
Input Sink
Input Source
IIH
IIL
1.0 µA
-1.0 µA
Output Voltage
Logic “1” Output Voltage
VOH1
VOH2
VDD=5V±10%, IOH=-3mA
2.4
VDD=3.3V±10%, IOH=-1mA 90% VDD
V
V
Logic “0” Output Voltage
VOL1
VOL2
VDD=5V±10%, IOL=1.8mA
VDD=3.3V±10%, IOH=1mA
0.4 V
10% VDD V
Standby Supply Current
IDDSB
VIN=VDD, Outputs Open
2.0 mA
Operating Supply Current
IDD f=1MHz, Outputs Open
10.0 mA
Input Capacitance
CIN
7.0 pF
Output Capacitance
COUT
10.0 pF
HOLT INTEGRATED CIRCUITS
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부품번호상세설명 및 기능제조사
HI-15530

5V / 3.3V Manchester Encoder / Decoder

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