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HI-3597 데이터시트 PDF




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기능 Octal ARINC 429 Receivers
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HI-3597 데이터시트, 핀배열, 회로
January, 2012
HI-3596, HI-3597, HI-3598, HI-3599
Octal ARINC 429 Receivers
with Label Recognition and SPI Interface
GENERAL DESCRIPTION
The HI-359x family from Holt Integrated Circuits are sili-
con gate CMOS ICs for interfacing up to eight ARINC
429 receive buses to a high-speed Serial Peripheral
Interface (SPI) enabled microcontroller. Each receiver
has user-programmable label recognition for up to 16
labels, a four-word data buffer (FIFO), and an on-chip
analog line receiver. Receive FIFO status can be moni-
tored using the programmable external interrupt pins,
or by polling the status register. Other features include
the ability to switch the bit-signifiance of the ARINC 429
label and to recognize the 32nd received ARINC bit as
either data or a parity flag. Some versions provide a digi-
tal transmit channel which can be utilized with an exter-
nal line driver such as HI-8570 to relay information from
multiple sources, for example sensors, to a single col-
lection point such as a flight computer and can also be
configured as a loopback test register for each receive
channel. Versions are also available with different input
resistance values to provide flexibility when using exter-
nal lightning protection circuitry. The SPI and all control
signals are CMOS and TTL compatible and support
3.3V or 5V operation.
32nd bit can be data or parity
Low Power
Industrial & extended temperature ranges
PIN CONFIGURATION (TOP VIEW)
ACLK - 1
SC__K - 2
CS - 3
SI - 4
SO - 5
MR - 6
TX1 - 7
TX0 - 8
RIN1A - 9
RIN1A-40 - 10
RIN1B-40 - 11
RIN1B - 12
- 13
HI-3598PQI
&
HI-3598PQT
39 - RIN8A
38 - RIN7B
37 - RIN7B-40
36 - RIN7A-40
35 - RIN7A
34 - RIN6B
33 - RIN6B-40
32 - RIN6A-40
31 - RIN6A
30 - RIN5B
29 - RIN5B-40
28 - RIN5A-40
27 - RIN5A
The HI-3596 and HI-3598 are full featured parts. The
HI-3597 and HI-3599 give the user the option of utilizing
a smaller 24-pin SOIC package with very little trade off in
features. In this case, a global interrupt flag is provided
instead of individual external FIFO interrupt pins. The
HI-3597 is identical to the HI-3599 except that it offers
the digital transmit feature and seven receive channels.
HI-3598 Full function, full pin-out version
52 - Pin Plastic Quad Flat Pack (PQFP)
FEATURES
ARINC 429 compliant
Up to 8 independent receive channels
Digital transmit channel (except HI-3599)
3.3V or 5.0V logic supply operation
On-chip analog line receivers connect directly to
ARINC 429 bus
Programmable label recognition for 16 labels per
channel
Independent data rate selection for each receiver
Four-wire SPI interface
Label bit-order control
ACLK - 1
SCK - 2
CS - 3
SI - 4
SO - 5
TX1 - 6
TX0 - 7
RIN2A - 8
RIN2B - 9
RIN3A - 10
RIN3B - 11
GND - 12
HI-3597
PSI
&
HI-3597
PST
24 - VDD
23 - FLAG
22 - RIN8B
21 - RIN8A
20 - RIN7B
19 - RIN7A
18 - RIN6B
17 - RIN6A
16 - RIN5B
15 - RIN5A
14 - RIN4B
13 - RIN4A
HI-3597 minimum footprint, reduced pin-out version
24 - Pin Plastic Small Outline package (SOIC)
(See page 13 for additional package pin configurations)
DS3598 Rev. C
HOLT INTEGRATED CIRCUITS
www.holtic.com
1
01/12




HI-3597 pdf, 반도체, 판매, 대치품
HI-3596, HI-3597, HI-3598, HI-3599
INSTRUCTIONS
Instruction op codes are used to read, write and con-
figure the HI-359x devices. The instruction format is
illustrated in Figure 2. When CS goes low, the next 8
clocks at the SCK pin shift an instruction op code into
the decoder, starting with the first rising edge. The op
code is fed into the SI pin, most significant bit first.
For write instructions, the most significant bit of the data
word must immediately follow the instruction op code
and is clocked into its register on the next rising SCK
edge. Data word length varies depending on word type
written: 16-bit Control Register writes, 32-bit transmit
register writes or 128-bit writes to a channel’s label-
matching enable/disable memory.
For read instructions, the most significant bit of the
requested data word appears at the SO pin after the last
op code bit is clocked into the decoder, at the next fall-
ing SCK edge. As in write instructions, the data field
bit-length varies with read instruction type.
Channel-specific instructions use the upper four bits to
specify an ARINC 429 receiver channel, 1-8 hex. The
lower four bits specify the op code, described in Table
2. The four channel assignment bits are “don’t care” for
instructions that are not channel-specific, such as Mas-
ter Reset.
ARINC 429
Channel
OP Code
MSB 7 6 5 4 3 2 1 0 LSB
SPI INSTRUCTION FORMAT
Example:
One SPI Instruction
CS
SCK
SI
MSB
LSB MSB
op code 14 hex
data field 0232 hex
ie: Load channel 1 control register with 0232 hex
LSB
Figure 2.  SPI Instruction Format
Table 2.  Defined Instructions
ARINC OP CODE
Channel Hex
X 0h
1h - 8h
1h
1h - 8h
1h - 8h
1h - 8h
1h - 8h
X
X
X
2h
3h
4h
5h
6h
7h
8h
X 9h
X Ah - Fh
DATA
FIELD
None
128 bits
128 bits
32 bits
16 bits
16 bits
16 bits
None
32 bits
32 bits
None
Description
Instruction not implemented. No operation.
Load label values to label memory. The data field consists of 16, 8-bit labels.
If fewer than 16 labels are needed for the application, the memory must be
padded with redundant (duplicate) label values.
Read the contents of the label memory for this channel.
Read an ARINC word from the receive FIFO for this channel. If the FIFO is
empty all zeros will be read.
Load the specified channel’s Control Register and clear that channel’s FIFO.
Read the specified channel’s Control Register.
Read the Status Register.
Master Reset (All channels).
Load the Transmit Register (High-speed data rate). This can also be used as
a test word for each receiver (Loopback self-test).
Load the Transmit Register (Low-speed data rate). This can also be used
as a test word for each receiver (Loopback self-test).
Instruction not implemented. No operation.
HOLT INTEGRATED CIRCUITS
4

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HI-3597 전자부품, 판매, 대치품
HI-3596, HI-3597, HI-3598, HI-3599
SCK
CS
SI
SO
SPI INTERFACE
FLAG
CONTROL BITS
CR2, CR6-8
FIFO
LOAD
CONTROL
4 words x 32-bit
FIFO
/ LABEL /
DECODE
COMPARE
ONES
NULL
ZEROS
16-label
Memory
EOS
32-BIT SHIFT REGISTER
DATA
PARITY
CHECK
32ND
BIT
BIT CLOCK
BIT
COUNTER
AND
END OF
SEQUENCE
SHIFT REGISTER
SHIFT REGISTER
WORD GAP
WORD GAP
TIMER
START
SEQUENCE
CONTROL
BIT CLOCK
END
SHIFT REGISTER
ERROR
DETECTION
ERROR
CLOCK
ACLK
Figure 4.  Receiver Block Diagram
The HI-359x family accept signals within these toler-
ances and rejects signals outside these tolerances.
Receiver logic achieves this as described below:
1. An accurate 1MHz clock source is required to vali-
date the receive signal timing. Less than 0.1% error
is recommended.
2. The receiver uses three separate 10-bit sampling
shift registers for Ones detection, Zeros detection
and Null detection. When the input signal is within
the differential voltage range for any shift register’s
state (One Zero or Null) sampling clocks a high bit
into that register. When the receive signal is outside
the differential voltage range defined for any shift
register, a low bit is clocked. Only one shift register
can clock a high bit for any given sample. All three
registers clock low bits if the differential input volt-
age is between defined state voltage bands.
Valid data bits require at least three consecutive
One or Zero samples (three high bits) in the upper
half of the Ones or Zeros sampling shift register, and
at least three consecutive Null samples (three high
bits) in the lower half of the Null sampling shift regis-
ter within the data bit interval.
A word gap Null requires at least three consecutive
Null samples (three high bits) in the upper half of the
Null sampling shift register and at least three con-
secutive Null samples (three high bits) in the lower
half of the Null sampling shift register. This guaran-
tees the minimum pulse width.
HOLT INTEGRATED CIRCUITS
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