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HI-3593 데이터시트 PDF




HOLTIC에서 제조한 전자 부품 HI-3593은 전자 산업 및 응용 분야에서
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부품번호 HI-3593 기능
기능 3.3V ARINC 429 Dual Receiver / Single Transmitter
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HI-3593 데이터시트, 핀배열, 회로
August 2013
HI-3593
3.3V ARINC 429 Dual Receiver,
Single Transmitter with SPI Interface
GENERAL DESCRIPTION
PIN CONFIGURATIONS (Top View)
The HI-3593 from Holt Integrated Circuits is a CMOS
integrated circuit for interfacing a Serial Peripheral
Interface (SPI) enabled microcontroller to the ARINC 429
serial bus. The device provides two receivers, each with
user-programmable label recognition for any combination
of 256 possible labels, 32 x 32 Receive FIFO, 3 priority-
label quick-access double-buffered registers and analog
line receiver. The independent transmitter has a 32 x 32
Transmit FIFO and built-in line driver. The line driver
operates from a single 3.3V supply and includes on-chip
DC/DC converter to generate the bipolar ARINC 429
differential voltage levels needed to directly drive the
ARINC 429 bus. The status of the transmit and receive
FIFOs and priority-label buffers can be monitored using
the programmable external interrupt pins, or by polling the
HI-3593 Status Registers. Other features include a
programmable option of data or parity in the 32nd bit, and
the ability to switch the bit-signifiance of ARINC 429 labels.
Pins are available with different input resistance and
output resistance values which provides flexibility when
using external lightning protection circuitry.
The Serial Peripheral Interface minimizes the number of
host interface signals resulting in a small footprint device
that can be interfaced to a wide range of industry-standard
microcontrollers supporting SPI. Alternatively, the SPI
signals may be controlled using just four general purpose
I/O port pins from a microcontroller or custom FPGA. The
SPI and all control signals are CMOS and TTL compatible
and support 3.3V operation.
The HI-3593 applies the ARINC 429 protocol to the
receivers and transmitter. ARINC 429 databus timing
comes from a 1 MHz clock input, or an internal counter can
derive it from higher clock frequencies having certain fixed
values, possibly the external host processor clock.
FEATURES
· ARINC 429 specification compliant
· Single 3.3V power supply
· On-chip analog line driver and receiver connect
directly to ARINC 429 bus
· Programmable label recognition for 256 labels
· 32 x 32 Receive FIFOs and Priority-Label buffers
· Independent data rates for Transmit and Receive
· 10MHz, four-wire Serial Peripheral Interface (SPI)
· Industrial & extended temperature ranges
-1
RIN1A-40 - 2
RIN1A - 3
RIN1B - 4
RIN1B-40 - 5
RIN2A-40 - 6
RIN2A - 7
RIN2B - 8
RIN2B-40 - 9
MR - 10
ACLK - 11
HI-3593PCI
HI-3593PCT
HI-3593PCM
33 - AMPA
32 - TXAOUT
31 - AMPB
30 - TXBOUT
29 -
28 - TFULL
27 - TEMPTY
26 - R1FLAG
25 - R1INT
24 - R2FLAG
23 - R2INT
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
-1
RIN1A-40 - 2
RIN1A - 3
RIN1B - 4
RIN1B-40 - 5
RIN2A-40 - 6
RIN2A - 7
RIN2B - 8
RIN2B-40 - 9
MR - 10
ACLK - 11
HI-3593PQI
HI-3593PQT
HI-3593PQM
33 - AMPA
32 - TXAOUT
31 - AMPB
30 - TXBOUT
29 -
28 - TFULL
27 - TEMPTY
26 - R1FLAG
25 - R1INT
24 - R2FLAG
23 - R2INT
44 - Pin Plastic Quad Flat Pack (PQFP)
(DS3593 Rev. B)
HOLT INTEGRATED CIRCUITS
www.holtic.com
08/13




HI-3593 pdf, 반도체, 판매, 대치품
HI-3593
TABLE 1. DEFINED INSTRUCTIONS
Op-Code R/W # Data
bytes
0x00
W0
0x04
W0
0x08
W1
0x0C
W4
0x10
W1
0x14
W 32
0x18
0x24
0x28
W3
W1
W 32
0x2C
0x34
0x38
0x40
0x44
0x48
0x4C
0x80
0x84
0x90
0x94
0x98
0x9C
0xA0
0xA4
0xA8
0xAC
0xB0
0xB4
0xB8
0xBC
0xC0
0xC4
0xC8
0xCC
0xD0
0xD4
0xFF
W3
W1
W1
W0
W0
W0
W0
R1
R1
R1
R1
R 32
R3
R4
R3
R3
R3
R1
R1
R 32
R3
R4
R3
R3
R3
R1
R1
R0
DESCRIPTION
Instruction not implemented. No operation.
Software controlled Master Reset
Write Transmit Control Register
Write ARINC 429 message to Transmit FIFO
Write Receiver 1 Control Register
Write label values to Receiver 1 label memory. Starting with label 0xFF, consecutively set or reset each
label in descending order. For example, if the first data byte is programmed to 10110010 then labels FF,
FD FC and F9 will be set and FE, FB, FA and F8 will be reset.
Write Receiver 1 Priority-Label Match Registers. The data field consists of three eight-bit labels. The first data
byte is written to P-L filter #3, the second to P-L filter #2, and the last byte to filter #1
Write Receiver 2 Control Register
Write label values to Receiver 2 label memory. Starting with label 0xFF, consecutively set or reset each
label in descending order. For example, if the first data byte is programmed to 10110010 then labels FF,
FD FC and F9 will be set and FE, FB, FA and F8 will be reset.
Write Receiver 2 Priority-Label Match Registers. The data field consists of three eight-bit labels. The first
eight bits is written to P-L filter #3, the second to P-L filter #2, and the last byte to filter #1
Write Flag / Interrupt Assignment Register
Write ACLK Division Register
Transmit current contents of Transmit FIFO if Transmit Control Register bit 5 (TMODE) is a “0”
Software Reset. Clears the Transmit and Receive FIFOs and the Priority-Label Registers
Set all bits in Receiver 1 label memory to a “1”
Set all bits in Receiver 2 label memory to a “1”
Read Transmit Status Register
Read Transmit Control Register
Read Receiver 1 Status Register
Read Receiver 1 Control Register
Read label values from Receiver 1 label memory.
Read Receiver 1 Priority-Label Match Registers.
Read one ARINC 429 message from the Receiver 1 FIFO
Read Receiver 1 Priority-Label Register #1, ARINC429 bytes 2,3 & 4 (bits 9 - 32)
Read Receiver 1 Priority-Label Register #2, ARINC429 bytes 2,3 & 4 (bits 9 - 32)
Read Receiver 1 Priority-Label Register #3, ARINC429 bytes 2,3 & 4 (bits 9 - 32)
Read Receiver 2 Status Register
Read Receiver 2 Control Register
Read label values from Receiver 2 label memory.
Read Receiver 2 Priority-Label Match Registers.
Read one ARINC 429 message from the Receiver 2 FIFO
Read Receiver 2 Priority-Label Register #1, ARINC429 bytes 2,3 & 4 (bits 9 - 32)
Read Receiver 2 Priority-Label Register #2, ARINC429 bytes 2,3 & 4 (bits 9 - 32)
Read Receiver 2 Priority-Label Register #3, ARINC429 bytes 2,3 & 4 (bits 9 - 32)
Read Flag / Interrupt Assignment Register
Read ACLK Division Register
Instruction not implemented. No operation.
HOLT INTEGRATED CIRCUITS
4

4페이지










HI-3593 전자부품, 판매, 대치품
HI-3593
FLAG / INTERRUPT ASSIGNMENT REGISTER
(Write, SPI Op-code 0x34)
(Read, SPI Op-code 0xD0)
76543210
MSB
LSB
Bit Name
7-6 R2INT[1:0]
R/W Default Description
R/W 0 The value of R2INT[1:0] defines the function of the R2INT output pin, as follows:
00 R2INT pulses high when a valid message is received and
placed in the Receiver 2 FIFO or any of the Receiver 2 Priority-
Label mail boxes
01 R2INT pulses high when a message is received in Receiver 2
Priority-Label mail box #1
10 R2INT pulses high when a message is received in Receiver 2
Priority-Label mail box #2
11 R2INT pulses high when a message is received in Receiver 2
Priority-Label mail box #3
5-4 R2FLAG[1:0] R/W 0 The value of R2FLAG[1:0] defines the function of the R2FLAG output pin, as follows:
00 R2FLAG goes high when Receiver 2 FIFO is empty
01 R2FLAG goes high when Receiver 2 FIFO contains 32 ARINC
429 words (FIFO is full)
10 R2FLAG goes high when Receiver 2 FIFO contains at least
sixteen ARINC 429 words (FIFO is half-full)
11 R2FLAG goes high when Receiver 2 FIFO contains one or more
words (FIFO is not empty)
3-2 R1INT[1:0] R/W 0 The value of R1INT[1:0] defines the function of the R1INT output pin, as follows:
00 R1INT pulses high when a valid message is received and
placed in the Receiver 1 FIFO or any of the Receiver 1 Priority-
Label mail boxes
01 R1INT pulses high when a message is received in Receiver 1
Priority-Label mail box #1
10 R1INT pulses high when a message is received in Receiver 1
Priority-Label mail box #2
11 R1INT pulses high when a message is received in Receiver 1
Priority-Label mail box #3
1-0 R1FLAG[1:0] R/W 0 The value of R1FLAG[1:0] defines the function of the R1FLAG output pin, as follows:
00 R1FLAG goes high when Receiver 1 FIFO is empty
01 R1FLAG goes high when Receiver 1 FIFO contains 32 ARINC
429 words (FIFO is full)
10 R1FLAG goes high when Receiver 1 FIFO contains at least
sixteen ARINC 429 words (FIFO is half-full)
11 R1FLAG goes high when Receiver 1 FIFO contains one or more
words (FIFO is not empty)
HOLT INTEGRATED CIRCUITS
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