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PDF HI-3584A Data sheet ( Hoja de datos )
| Número de pieza | HI-3584A | |
| Descripción | ARINC 429 3.3V Serial Transmitter and Dual Receiver | |
| Fabricantes | HOLTIC | |
| Logotipo |  |
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July 2013
HI-3584A
ARINC 429 3.3V Serial Transmitter
and Dual Receiver with High-Speed Interface
GENERAL DESCRIPTION
The HI-3584A from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a 16-bit parallel data bus to the
ARINC 429 serial bus. The HI-3584A design offers a high-
speed host CPU interface compared with the earlier HI-
3584 product. The device provides two receivers each with
label recognition, a 32 by 32 FIFO, and an analog line
receiver. Up to 16 labels may be programmed for each
receiver. The independent transmitter also has a 32 by 32
FIFO. The status of all three FIFOs can be monitored using
the external status pins or by polling the HI-3584A’s status
register.
Other features include a programmable option of data or
parity in the 32nd bit, and the ability to unscramble the 32 bit
word. Also, versions are available with different values of
input resistance to allow users to more easily add external
lightning protection circuitry.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The databus and all control
signals are CMOS and TTL compatible.
The HI-3584A applies the ARINC protocol to the receivers
and transmitter. Timing is based on a 1 Megahertz clock.
Additional interface circuitry such as the Holt HI-8570 or
HI-8571 is required to translate the transmitter’s 3.3 volt
logic outputs to ARINC 429 drive levels.
FEATURES
• ARINC specification 429 compatible
• 3.3V logic supply operation
• Dual receiver and transmitter interface
• Analog line receivers connect directly to ARINC bus
• Programmable label recognition
• On-chip 16 label memory for each receiver
• 32 x 32 FIFOs each receiver and transmitter
• Independent data rate selection for transmitter
and each receiver
• Status register
• Data scramble control
• 32nd transmit bit can be data or parity
• Self test mode
• Low power
• Industrial & Extended temperature ranges
APPLICATIONS
• Avionics data communication
• Serial to parallel conversion
• Parallel to serial conversion
PIN CONFIGURATIONS (Top View)
(See page 13 for additional pin configuration)
See Note below
N/C - 1
D/R1 - 2
FF1 - 3
HF1 - 4
D/R2 - 5
FF2 - 6
HF2 - 7
SEL - 8
EN1 - 9
EN2 - 10
N/C - 11
BD15 - 12
BD14 - 13
BD13 - 14
BD12 - 15
BD11 - 16
HI-3584APCI
HI-3584APCT
&
HI-3584APCM
48 - CWSTR
47 - ENTX
46 - 429DO
45 - N/C
44 - N/C
43 - N/C
42 - N/C
41 - 429DO
40 - FFT
39 - HFT
38 - TX/R
37 - PL2
36 - PL1
35 - BD00
34 - BD01
33 - N/C
(Note: All 3 VDD pins must be connected to the same 3.3V supply)
64 - Pin Plastic 9mm x 9mm
Chip-Scale Package
FF1 - 1
HF1 - 2
D/R2 - 3
FF2 - 4
HF2 - 5
SEL - 6
EN1 - 7
EN2 - 8
BD15 - 9
BD14 - 10
BD13 - 11
BD12 - 12
BD11 - 13
HI-3584APQI
HI-3584APQT
&
HI-3584APQM
39 - N/C
38 - CWSTR
37 - ENTX
36 - N/C
35 - 429DO
34 - 429DO
33 - N/C
32 - FFT
31 - HFT
30 - TX/R
29 - PL2
28 - PL1
27 - BD00
52 - Pin Plastic Quad Flat Pack (PQFP)
(DS3584A Rev. C)
HOLT INTEGRATED CIRCUITS
www.holtic.com
07/13
1 page  
HI-3584A
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER PARITY
The 32nd bit of received ARINC words stored in the receive FIFO
is used as a Parity Flag indicating whether good Odd parity is
received from the incoming ARINC word.
Odd Parity Received
The parity bit is reset to indicate correct parity was received
and the resulting word is then written to the receive FIFO.
Even Parity Received
The receiver sets the 32nd bit to a “1”, indicating a parity error
and the resulting word is then written to the receive FIFO.
Therefore, the 32nd bit retrieved from the receiver FIFO will
always be “0” when valid (odd parity) ARINC 429 words are
received.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending upon the state of control
register bits CR2-CR11, the received ARINC 32-bit word is then
checked for correct decoding and label matching before being
loaded into the 32 x 32 receive FIFO.
ARINC words which do not meet the necessary 9th and 10th
ARINC bit or label matching are ignored and are not loaded into
the receive FIFO. The following table describes this operation.
CR2(3) ARINC word CR6(9) ARINC word
matches
bits 9,10
label
match
CR7,8 (10,11)
FIFO
0 X0 X
1 No 0
X
1 Yes 0
X
0 X 1 No
0 X 1 Yes
1 Yes 1
No
1 No 1 Yes
1 No 1 No
1 Yes 1 Yes
Load FIFO
Ignore data
Load FIFO
Ignore data
Load FIFO
Ignore data
Ignore data
Ignore data
Load FIFO
SEL
EN
MUX
CONTROL
TO PINS
32 TO 16 DRIVER
R/W
CONTROL
CONTROL
BITS
HF
FF
D/R
FIFO
LOAD
CONTROL
CONTROL
BIT
32 X 32
FIFO
/ LABEL /
DECODE
COMPARE
CONTROLBITS
CR0, CR14
CLOCK
OPTION
16 x 8
LABEL
MEMORY
EOS
32 BIT SHIFT REGISTER
DATA PARITY
CHECK
BIT CLOCK
32ND
BIT
BIT
COUNTER
AND
END OF
SEQUENCE
ONES
NULL
SHIFT REGISTER
SHIFT REGISTER
WORD GAP
WORD GAP
TIMER
BIT CLOCK
START
SEQUENCE
CONTROL
END
CLOCK
ZEROS
SHIFT REGISTER
ERROR
DETECTION
ERROR
CLOCK
FIGURE 2. RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
5
CLK
5 Page 
HI-3584A
ABSOLUTE MAXIMUM RATINGS
Supply Voltages VDD ........................................... -0.3V to +4V Power Dissipation at 25°C .......................................... 500 mW
Voltage at pins RIN1A, RIN1B, RIN2A, RIN2B ... -120V to +120V DC Current Drain per pin .............................................. ±10mA
Voltage at any other pin ............................... -0.3V to VDD +0.3V Storage Temperature Range ........................ -65°C to +150°C
Solder temperature (Reflow) ............................................ 260°C Operating Temperature Range (Industrial): .... -40°C to +85°C
(Extended): .. -55°C to +125°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VDD = 3.3V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
ARINC INPUTS - Pins RIN1A, RIN1B, RIN2A, RIN2B
SYMBOL
CONDITIONS
LIMITS
UNIT
MIN TYP MAX
Differential Input Voltage:
(RIN1A to RIN1B, RIN2A to RIN2B)
ONE
ZERO
NULL
VIH
VIL
VNUL
Common mode voltage
less than ±4V with
with respect to GND
6.5
-13.0
-2.5
10.0
-10.0
0
13.0
-6.5
2.5
V
V
V
Input Resistance:
Differential
To GND
To VDD
RI
RG
RH
12 80
12 45
12 45
KW
KW
KW
Input Current:
Input Sink
Input Source
IIH
IIL
-450
200 µA
µA
Input Capacitance:
(Guaranteed but not tested)
Differential
To GND
To VDD
CI (RIN1A to RIN1B, RIN2A to RIN2B)
CG
CH
20 pF
20 pF
20 pF
BI-DIRECTIONAL INPUTS - Pins BD00 - BD15
Input Voltage:
Input Voltage HI
Input Voltage LO
VIH
VIL
70%
VDD
30% VDD
Input Current:
Input Sink
Input Source
IIH
IIL
1.5 µA
-1.5 µA
OTHER INPUTS
Input Voltage:
Input Voltage HI
Input Voltage LO
VIH
VIL
70%
30%
V
V
Input Current:
Input Sink
Input Source
Pull-down Current (TEST pin)
Pull-up Current (RSR pin)
IIH
IIL
IPD
IPU
1.5 µA
-1.5 µA
330 µA
-330
µA
Input Capacitance:
(Guaranteed but not tested)
CI
15 pF
OUTPUTS
Output Voltage:
Logic "1" Output Voltage
Logic "0" Output Voltage
VOH
VOL
IOH = -100µA
IOL = 1.0mA
VDD - 0.2V
10%VDD
V
V
Output Current:
(All Outputs & Bi-directional Pins)
Output Sink
Output Source
IOL
IOH
VOUT = 0.4V
VOUT = VDD - 0.4V
1.6
mA
-1.0 mA
Output Capacitance:
CO
15 pF
Operating Supply Current
VDD
IDD 3.5 7 mA
HOLT INTEGRATED CIRCUITS
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet HI-3584A.PDF ] | |
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