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HI-3583A 데이터시트, 핀배열, 회로
July 2013
HI-3582A, HI-3583A
ARINC 429
3.3V Terminal IC with High-Speed Interface
GENERAL DESCRIPTION
The HI-3582A/HI-3583A from Holt Integrated Circuits are
silicon gate CMOS devices for interfacing a 16-bit parallel
data bus directly to the ARINC 429 serial bus. The
HI-3582A/HI-3583A design offers a high-speed host CPU
interface compared with the earlier HI-3582/HI-3583
products. The device provides two receivers each with
label recognition, 32 by 32 FIFO, and analog line receiver.
Up to 16 labels may be programmed for each receiver.
The independent transmitter has a 32 X 32 FIFO and a
built-in line driver. The status of all three FIFOs can be
monitored using the external status pins, or by polling the
HI-3582A/HI-3583A status register. Other features include
a programmable option of data or parity in the 32nd bit,
and the ability to unscramble the 32 bit word. Also,
versions are available with different values of input
resistance and output resistance to allow users to more
easily add external lightning protection circuitry.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The databus and all control
signals are 3.3V CMOS compatible.
The HI-3582A/HI-3583A apply the ARINC protocol to the
receivers and transmitter. Timing is based on a 1 Mega-
hertz clock.
APPLICATIONS
• Avionics data communication
• Serial to parallel conversion
• Parallel to serial conversion
PIN CONFIGURATIONS (Top View)
(See page 14 for additional pin configuration)
See Note below
N/C - 1
D/R1 - 2
FF1 - 3
HF1 - 4
D/R2 - 5
FF2 - 6
HF2 - 7
SEL - 8
EN1 - 9
EN2 - 10
N/C - 11
BD15 - 12
BD14 - 13
BD13 - 14
BD12 - 15
BD11 - 16
HI-3582APCI
HI-3582APCT
HI-3582APCM
&
HI-3583APCI
HI-3583APCT
HI-3583APCM
48 - CWSTR
47 - ENTX
46 - N/C
45 - V+
44 - TXBOUT
43 - TXAOUT
42 - V-
41 - N/C
40 - FFT
39 - HFT
38 - TX/R
37 - PL2
36 - PL1
35 - BD00
34 - BD01
33 - N/C
(Note: All 3 VDD pins must be connected to the same 3.3V supply)
64 - Pin Plastic 9mm x 9mm
Chip-Scale Package
FEATURES
· ARINC specification 429 compatible
· High-speed 3.3V logic interface
· Dual receiver and transmitter interface
· Analog line driver and receivers connect directly to
ARINC bus
· Programmable label recognition
· On-chip 16 label memory for each receiver
· 32 x 32 FIFOs each receiver and transmitter
· Independent data rate selection for transmitter and
each receiver
· Status register
· Data scramble control
· 32nd transmit bit can be data or parity
· Self test mode
· Low power
· Industrial & extended temperature ranges
FF1 - 1
HF1 - 2
D/R2 - 3
FF2 - 4
HF2 - 5
SEL - 6
EN1 - 7
EN2 - 8
BD15 - 9
BD14 - 10
BD13 - 11
BD12 - 12
BD11 - 13
HI-3582APQI
HI-3582APQT
HI-3582APQM
&
HI-3583APQI
HI-3583APQT
HI-3583APQM
39 - N/C
38 - CWSTR
37 - ENTX
36 - V+
35 - TXBOUT
34 - TXAOUT
33 - V-
32 - FFT
31 - HFT
30 - TX/R
29 - PL2
28 - PL1
27 - BD00
(DS3582A Rev. C)
52 - Pin Plastic Quad Flat Pack (PQFP)
HOLT INTEGRATED CIRCUITS
www.holtic.com
07/13




HI-3583A pdf, 반도체, 판매, 대치품
HI-3582A, HI-3583A
FUNCTIONAL DESCRIPTION (cont.)
ARINC 429 DATA FORMAT
Control register bit CR15 is used to control how individual bits in the
received or transmitted ARINC word are mapped to the HI-3582A/
HI-3583A data bus during data read or write operations. The
following table describes this mapping:
BYTE 1
DATA BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
BUS 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC 13 12 11 10 9 31 30 32 1 2 3 4 5 6 7 8
BIT
CR15=0
ARINC 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
BIT
CR15=1
BYTE 2
DATA BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
BUS 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC
BIT
CR15=0
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
ARINC
BIT
CR15=1
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
THE RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
The HI-3582A/HI-3583A guarantee recognition of these levels with a
common mode Voltage with respect to GND less than ±4V for the
worst case condition (3.0V supply and 13V signal level).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
RECEIVER LOGIC OPERATION
Figure 2 shows a block diagram of the logic section of each receiver.
BIT TIMING
The ARINC 429 specification contains the following timing specifi-
cation for the received data:
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
HIGH SPEED LOW SPEED
100K BPS ± 1% 12K -14.5K BPS
1.5 ± 0.5 µsec 10 ± 5 µsec
1.5 ± 0.5 µsec 10 ± 5 µsec
5 µsec ± 5% 34.5 to 41.7 µsec
The HI-3582A/HI-3583A accept signals that meet these specifica-
tions and rejects signals outside the tolerances. The way the logic
operation achieves this is described below:
1. Key to the performance of the timing checking logic is an
accurate 1MHz clock source. Less than 0.1% error is recom-
mended.
2. The sampling shift registers are 10 bits long and must
show three consecutive Ones, Zeros or Nulls to be consid-
ered valid data. Additionally, for data bits, the One or Zero in
the upper bits of the sampling shift registers must be followed
by a Null in the lower bits within the data bit time. For a Null in
the word gap, three consecutive Nulls must be found in both
the upper and lower bits of the sampling shift register. In this
manner the minimum pulse width is guaranteed.
3. Each data bit must follow its predecessor by not less than
8 samples and no more than 12 samples. In this manner the
bit rate is checked. With exactly 1MHz input clock frequency,
the acceptable data bit rates are as follows:
RIN1A
OR
RIN2A
RIN1B
OR
RIN2B
vDD
GND
vDD
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
ONES
NULL
ZEROES
DATA BIT RATE MIN
DATA BIT RATE MAX
HIGH SPEED LOW SPEED
83K BPS
125K BPS
10.4K BPS
15.6K BPS
4. The Word Gap timer samples the Null shift register every
10 input clocks (80 for low speed) after the last data bit of a
valid reception. If the Null is present, the Word Gap counter
is incremented. A count of 3 will enable the next reception.
GND
FIGURE 1. ARINC RECEIVER INPUT
HOLT INTEGRATED CIRCUITS
4

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HI-3583A 전자부품, 판매, 대치품
HI-3582A, HI-3583A
FUNCTIONAL DESCRIPTION (cont.)
DATA TRANSMISSION
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at TXAOUT and TXBOUT. The 31 or 32 bits in
the data transmission shift register are presented sequentially to
the outputs in the ARINC 429 format with the following timing:
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
HIGH SPEED
10 Clocks
5 Clocks
5 Clocks
40 Clocks
LOW SPEED
80 Clocks
40 Clocks
40 Clocks
320 Clocks
The word counter detects when all loaded positions have been
transmitted and sets the transmitter ready flag, TX/R, high.
TRANSMITTER PARITY
The parity generator counts the Ones in the 31-bit word. If
control register bit CR12 is set low, the 32nd bit transmitted will
make parity odd. If the control bit is high, the parity is even.
Setting CR4 to a Zero bypasses the parity generator, and allows
32 bits of data to be transmitted.
SELF TEST
If control register bit CR5 is set low, the transmitter serial output
data are internally connected to each of the two receivers,
bypassing the analog interface circuitry. Data is passed
unmodified to receiver 1 and inverted to receiver 2. Taking TEST
high forces TXAOUT and TXBOUT into the null state regardless
of the state of CR5.
SYSTEM OPERATION
The two receivers are independent of the transmitter.
Therefore, control of data exchanges is strictly at the option of
the user. The only restrictions are:
1. The received data will be overwritten if the receiver FIFO
is full and at least one location is not retrieved before the next
complete ARINC word is received.
2. The transmitter FIFO can store 32 words maximum and
ignores attempts to load additional data if full.
LINE DRIVER OPERATION
The line driver in the HI-3582A/HI-3583A are designed to directly
drive the ARINC 429 bus. The two ARINC outputs (TXAOUT
and TXBOUT) provide a differential voltage to produce a +10 volt
One, a -10 volt Zero, and a 0 volt Null. Control register bit CR13
controls both the transmitter data rate, and the slope of the
differential output signal. No additional hardware is required to
control the slope. Programming CR13 to Zero causes a
100 kbits/s data rate and a slope of 1.5 µs on the ARINC outputs;
a One on CR13 causes a 12.5 kbit/s data rate and a slope of
10 µs. Timing is set by on-chip resistor and capacitor and tested
to be within ARINC requirements.
The HI-3582A has 37.5 ohms in series with each line driver output.
The HI-3583A has 10 ohms in series. The HI-3583A is for
applications where external series resistance is needed, typically
for lightning protection devices.
REPEATER OPERATION
Repeater mode of operation allows a data word that has been
received by the HI-3582A/HI-3583A to be placed directly into the
transmitter FIFO. Repeater operation is similar to normal receiver
operation. In normal operation, either byte of a received data word
may be read from the receiver latches first by use of SEL input.
During repeater operation however, the lower byte of the data word
must be read first. This is necessary because, as the data is being
read, it is also being loaded into transmitter FIFO which is always
loaded with the lower byte of the data word first. Signal flow for
repeater operation is shown in the Timing Diagrams section.
HI-3582A-15 and HI-3583A-15
The HI-3582A-15/HI-3583A-15 options are similar to the HI-3582A/
HI-3583A with the exception that they allow an external 15 Kohm
resistor to be added in series with each ARINC input without affect-
ing the ARINC input thresholds. This option is especially useful in
applications where lightning protection circuitry is also required.
Each side of the ARINC bus must be connected through a
15 Kohm series resistor in order for the chip to detect the correct
ARINC levels. The typical 10 volt differential signal is translated
and input to a window comparator and latch. The comparator lev-
els are set so that with the external 15 Kohm resistors, they are
just below the standard 6.5 volt minimum ARINC data threshold
and just above the standard 2.5 volt maximum ARINC null thresh-
old.
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
line drivers and line receivers.
HIGH SPEED OPERATION
The HI-3582A and HI-3583A may be operated at clock frequencies
beyond that required for ARINC compliant operation. For operation
at Master Clock (CLK) frequencies up to 5MHz, please contact
Holt applications engineering.
MASTER RESET (MR)
On a Master Reset data transmission and reception are immedi-
ately terminated, all three FIFOs are cleared as are the FIFO flags
at the device pins and in the Status Register. The Control
Register is not affected by a Master Reset.
HOLT INTEGRATED CIRCUITS
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