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HI-6132 데이터시트 PDF




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부품번호 HI-6132 기능
기능 3.3V BC / MT / RT Multi-Terminal Device
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HI-6132 데이터시트, 핀배열, 회로
October, 2016
HI-6130 / HI-6131 / HI-6132
MIL-STD-1553 / MIL-STD-1760
3.3V BC / MT / RT Multi-Terminal Device
GENERAL DESCRIPTION
The 3.3V CMOS HI-613x device provides a complete
single- or multi-function interface between a host
processor and MIL-STD-1553B bus. Each IC contains
a Bus Controller (BC), a Bus Monitor Terminal (MT)
and two independent Remote Terminals (RTs). Any
combination of the contained 1553 functions can
be enabled for concurrent operation. The enabled
terminals communicate with the MIL-STD-1553 buses
through a shared on-chip dual bus transceiver and
external transformer. The user allocates 64K bytes of
on-chip static RAM between devices to suit application
requirements.
Two options are offered for host access to internal
registers and static RAM: The HI-6130 uses a 16-bit
parallel bus; the HI-6131 communicates with the host
via a 4-wire serial peripheral interface (SPI). The HI-
6132 combines both 16-bit parallel bus and SPI in a
single 15 x 15mm hermetically sealed ceramic package.
Device
Host Interface Packages
HI-6130
HI-6131
HI-6132
16-bit parallel
4-wire SPI
16-bit parallel
or 4-wire SPI
100-pin PQFP
64-pin QFN
64-pin PQFP
121 ceramic BGA
or PGA
Programmable interrupts provide terminal status
to the host processor. Circular data buffers in RAM
have interrupts for rollover and programmable “level
attained”. The HI-613x can be configured for automatic
self-initialization after reset. A dedicated SPI port reads
data from an external serial EEPROM to fully configure
registers and RAM for any subset of one to four terminal
devices.
FEATURES
Concurrent multi-terminal operation for one to
four MIL-STD-1553B functions: BC, MT and two
independent RTs.
64K bytes internal static RAM with RAM Error
Detection/Correction option.
Autonomous terminal operation requires minimal
host intervention.
Shared MIL-STD-1553 bus interface reduces
circuit complexity and circuit board area.
Fully programmable Bus Controller with 28 op
code instruction set.
Simple Monitor Terminal (SMT) Mode records
commands and data separately, with 16-bit or 48-
bit time tagging.
IRIG Monitor Terminal (IMT) Mode supports IRIG-
106 Chapter 10 packet format.
IMT Monitor Mode can optionally generate
complete IRIG-106 data packets, including full
packet headers and trailers.
Independent 16-bit time tag counters and clock
sources for all terminals. The Bus Controller
and Monitor also have 32- and 48-bit time count
options, respectively.
64-Word Interrupt Log Buffer queues the most
recent 32 interrupts. Hardware-assisted interrupt
decoding quickly identifies interrupt sources.
Built-in self-test for protocol logic, digital signal
paths and internal RAM.
Optional self-initialization at reset uses external
serial EEPROM.
±8kV ESD Protection (HBM, all pins).
Two temperature ranges: -40oC to +85oC, or
-55oC to +125oC with optional burn-in.
RoHS compliant.
PIN CONFIGURATION (TOP)
VCC - 1
GND - 2
BCTRIG - 3
D12 - 4
D13 - 5
D14 - 6
D15 - 7
RAMEDC - 8
CE - 9
MODE - 10
STR / OE - 11
VCC - 12
MCLK - 13
GND - 14
WAIT / WAIT - 15
R/W / WE - 16
RT1A_0 - 17
RT1A_1 - 18
RT1A_2 - 19
MR - 20
RT1A_3 - 21
RT1A_4 - 22
A0 - 23
A1 - 24
A2 - 25
HI-6130PQxF
TOP VIEW
75 - D1
74 - D0
73 - WPOL
72 - BTYPE
71 - BENDI
70 - TEST
69 - RT1LOCK
68 - MTSTOFF
67 - BCENA
66 - BUSA
65 - VCCP
64 - BUSA
63 - BUSB
62 - VCCP
61 - BUSB
60 - RT2ENA
59 - RT2A_0
58 - RT2A_1
57 - RT2A_2
56 - RT2A_3
55 - BWID
54 - A15
53 - A14
52 - A12
51 - A13
DS6130 Rev. S
HOLT INTEGRATED CIRCUITS
www.holtic.com
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10/16




HI-6132 pdf, 반도체, 판매, 대치품
HI-6130, HI-6131
7. REGISTER & MEMORY ADDRESSING........................................................... 25
7.1. 8-bit Bus Operation: (HI-6130 Only).......................................................................... 25
8. REGISTER DEFINITIONS................................................................................ 25
9. REGISTERS USED BY ALL DEVICE FUNCTIONS......................................... 30
9.1. Master Configuration Register (0x0000).................................................................... 30
9.2. Master Status and Reset Register (0x0001) ............................................................. 34
9.3. Overview of Interrupts................................................................................................ 37
9.4. Hardware Interrupt Behavior...................................................................................... 37
9.5. Interrupt Count & Log Address Register (0x000A) .................................................... 38
9.6. Interrupt Log Buffer.................................................................................................... 39
9.7. Hardware Interrupt Registers..................................................................................... 41
9.7.1. Hardware Interrupt Enable Register (0x000F) ....................................................... 41
9.7.2. Hardware Pending Interrupt Register (0x0006) ..................................................... 41
9.7.3. Hardware Interrupt Output Enable Register (0x0013) ........................................... 41
9.8. Extended Configuration Register (0x004D)............................................................... 45
9.9. Time Tag Counter Configuration................................................................................ 47
9.10. Time Tag Counter Configuration Register (0x0039)................................................... 48
9.11. Memory Address Pointer Registers (HI-6131 only).................................................... 52
10. BUS CONTROLLER − CONFIGURATION AND OPERATION......................... 54
10.1. Bus Controller Condition Codes................................................................................. 55
10.2. Bus Controller Instruction Op Codes......................................................................... 58
10.3. Bus Controller General Purpose Queue.................................................................... 66
10.4. Bus Controller Message Control / Status Blocks....................................................... 66
10.4.1. BC Control Word.................................................................................................... 67
10.4.2. Time to Next Message Word.................................................................................. 71
10.4.3. Data Block Pointer.................................................................................................. 71
10.4.4. BC Block Status Word............................................................................................ 72
11. BUS CONTROLLER REGISTER DESCRIPTION ........................................... 76
11.1. BC (Bus Controller) Configuration Register (0x0032)................................................ 76
11.2. Start Address Register for Bus Controller (BC) Instruction List (0x0033).................. 85
11.3. Bus Controller (BC) Instruction List Pointer (0x0034)................................................ 85
11.4. Bus Controller (BC) Frame Time Remaining Register (0x0035)................................ 86
11.5. Bus Controller (BC) Time To Next Message Register (0x0036)................................. 86
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HI-6132 전자부품, 판매, 대치품
HI-6130, HI-6131
16.6.1. Practical IRIG-106 packet word count considerations.......................................... 137
16.7. IMT Maximum Packet Time Register (0x002C)....................................................... 137
16.7.1. Practical IRIG-106 packet time considerations..................................................... 137
16.8. IMT Packet Maximum Gap Time Register (0x002D)............................................... 137
16.8.1. Practical IRIG-106 maximum gap time considerations......................................... 138
16.9. IMT Packet Header Channel ID Register (0x002E)................................................. 138
16.10. IMT Monitor Time Tag Count Low Register (0x003A).............................................. 139
16.11. IMT Monitor Time Tag Count Mid Register (0x003B)............................................... 139
16.12. IMT Monitor Time Tag Count High Register (0x003C)............................................. 139
16.13. IMT Time Tag Utility Low Register (0x003D)............................................................ 139
16.14. IMT Time Tag Utility Mid Register (0x003E)............................................................. 140
16.15. IMT Time Tag Utility High Register (0x003F)........................................................... 140
16.15.1. Loading a 48-bit value into the three 16-bit IMT Time Tag Count Registers ........ 140
16.15.2. Capturing a 48-bit value from the three 16-bit IMT Time Tag Count Registers ... 140
16.16. IMT Time Tag Match Low Register (0x0040)........................................................... 140
16.17. IMT Time Tag Match Mid Register (0x0041)............................................................ 140
16.18. IMT Time Tag Match High Register (0x0042)........................................................... 141
16.19. IMT Bus Monitor Interrupt Registers and Their Use................................................. 142
16.19.1. IMT Bus Monitor Interrupt Enable Register (0x0011)........................................... 143
16.19.2. IMT Bus Monitor Pending Interrupt Register (0x0008)......................................... 143
16.19.3. IMT Bus Monitor Interrupt Output Enable Register (0x0015)............................... 143
17. SINGLE OR DUAL REMOTE TERMINAL(S) − OVERVIEW ......................... 146
18. REGISTERS USED BY REMOTE TERMINALS RT1 AND RT2..................... 147
18.1. Remote Terminal 1 (RT1) Configuration Register (0x0017)
Remote Terminal 2 (RT2) Configuration Register (0x0020)..................................... 147
18.2. Remote Terminal 1 (RT1) Operational Status Register (0x0018)
Remote Terminal 2 (RT2) Operational Status Register (0x0021)............................ 151
18.3. Remote Terminal 1 (RT1) Current Command Register (0x0002)
Remote Terminal 2 (RT2) Current Command Register (0x0004)............................. 153
18.4. Remote Terminal 1 (RT1) Current Control Word Address Register (0x0003)
Remote Terminal 2 (RT2) Current Control Word Address Register (0x0005).......... 153
18.5. Remote Terminal 1 (RT1) Descriptor Table Base Address Register (0x0019)
Remote Terminal 2 (RT2) Descriptor Table Base Address Register (0x0022)......... 153
18.6. Remote Terminal 1 (RT1) MIL-STD-1553 Status Word Bits Register (0x001A)
Remote Terminal 2 (RT2) MIL-STD-1553 Status Word Bits Register (0x0023)....... 154
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관련 데이터시트

부품번호상세설명 및 기능제조사
HI-6130

3.3V BC / MT / RT Multi-Terminal Device

HOLTIC
HOLTIC
HI-6131

3.3V BC / MT / RT Multi-Terminal Device

HOLTIC
HOLTIC

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