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VND7030AJ 데이터시트 PDF




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기능 Double channel high-side driver
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VND7030AJ 데이터시트, 핀배열, 회로
VND7030AJ
Double channel high-side driver with MultiSense analog
feedback for automotive applications
Datasheet - production data
Loss of ground and loss of VCC
Reverse battery with external
components
Electrostatic discharge protection
Features
Max transient supply voltage
Operating voltage range
Typ. on-state resistance (per Ch)
Current limitation (typ)
Standby current (max)
VCC 40 V
VCC 4 to 28 V
RON 31
ILIMH 56 A
ISTBY 0.5 µA
Automotive qualified
General
Double channel smart high-side driver
with MultiSense analog feedback
Very low standby current
Compatible with 3 V and 5 V CMOS
outputs
MultiSense diagnostic functions
Multiplexed analog feedback of: load
current with high precision proportional
current mirror, VCC supply voltage and
TCHIP device temperature
Overload and short to ground (power
limitation) indication
Thermal shutdown indication
OFF-state open-load detection
Output short to VCC detection
Sense enable/disable
Protections
Undervoltage shutdown
Overvoltage clamp
Load current limitation
Self limiting of fast thermal transients
Configurable latch-off on
overtemperature or power limitation
with dedicated fault reset pin
Applications
All types of Automotive resistive, inductive
and capacitive loads
Specially intended for automotive signal
lamps (up to 2 x P21W or SAE1156 and
R5W paralleled or LED rear combinations)
Description
The device is a double channel high-side driver
manufactured using ST proprietary VIPower® M0-
7 technology and housed in PowerSSO-16
package. The device is designed to drive 12 V
automotive grounded loads through a 3 V and
5 V CMOS-compatible interface, providing
protection and diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown with configurable
latch-off.
A FaultRST pin unlatches the output in case of
fault or disables the latch-off functionality.
A dedicated multifunction multiplexed analog
output pin delivers sophisticated diagnostic
functions including high precision proportional
load current sense, supply voltage feedback and
chip temperature sense, in addition to the
detection of overload and short circuit to ground,
short to VCC and OFF-state open-load.
A sense enable pin allows OFF-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices.
May 2015
DocID027403 Rev 1
1/46
This is information on a product in full production.
www.st.com




VND7030AJ pdf, 반도체, 판매, 대치품
List of figures
List of figures
VND7030AJ
Figure 1: Block diagram ..............................................................................................................................5
Figure 2: Configuration diagram (top view).................................................................................................6
Figure 3: Current and voltage conventions.................................................................................................7
Figure 4: IOUT/ISENSE versus IOUT.......................................................................................................16
Figure 5: Current sense accuracy versus IOUT .......................................................................................16
Figure 6: Switching time and Pulse skew .................................................................................................17
Figure 7: MultiSense timings (current sense mode) .................................................................................17
Figure 8: Multisense timings (chip temperature and VCC sense mode) ..................................................18
Figure 9: TDSTKON..................................................................................................................................18
Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ......................20
Figure 11: Latch functionality - behavior in hard short circuit condition....................................................20
Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) ....21
Figure 13: Standby mode activation .........................................................................................................21
Figure 14: Standby state diagram.............................................................................................................22
Figure 15: OFF-state output current .........................................................................................................22
Figure 16: Standby current .......................................................................................................................22
Figure 17: IGND(ON) vs. Iout ...................................................................................................................23
Figure 18: Logic Input high level voltage ..................................................................................................23
Figure 19: Logic Input low level voltage....................................................................................................23
Figure 20: High level logic input current ...................................................................................................23
Figure 21: Low level logic input current ....................................................................................................23
Figure 22: Logic Input hysteresis voltage .................................................................................................23
Figure 23: FaultRST Input clamp voltage .................................................................................................24
Figure 24: Undervoltage shutdown...........................................................................................................24
Figure 25: On-state resistance vs. Tcase .................................................................................................24
Figure 26: On-state resistance vs. VCC ...................................................................................................24
Figure 27: Turn-on voltage slope..............................................................................................................24
Figure 28: Turn-off voltage slope..............................................................................................................24
Figure 29: Won vs. Tcase.........................................................................................................................25
Figure 30: Woff vs. Tcase.........................................................................................................................25
Figure 31: ILIMH vs. Tcase.......................................................................................................................25
Figure 32: OFF-state open-load voltage detection threshold ...................................................................25
Figure 33: Vsense clamp vs. Tcase..........................................................................................................25
Figure 34: Vsenseh vs. Tcase ..................................................................................................................25
Figure 35: Application diagram .................................................................................................................27
Figure 36: Simplified internal structure .....................................................................................................27
Figure 37: MultiSense and diagnostic – block diagram ............................................................................29
Figure 38: MultiSense block diagram .......................................................................................................30
Figure 39: Analogue HSD – open-load detection in off-state ...................................................................31
Figure 40: Open-load / short to VCC condition.........................................................................................32
Figure 41: GND voltage shift ....................................................................................................................33
Figure 42: Maximum turn off current versus inductance ..........................................................................35
Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) ............................................36
Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ...........................................36
Figure 45: Rthj-amb vs PCB copper area in open box free air condition (one channel on) .....................37
Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) ..............37
Figure 47: Thermal fitting model of a double-channel HSD in PowerSSO-16..........................................38
Figure 48: PowerSSO-16 package dimensions........................................................................................39
Figure 49: PowerSSO-16 reel 13" ............................................................................................................41
Figure 50: PowerSSO-16 carrier tape ......................................................................................................42
Figure 51: PowerSSO-16 schematic drawing of leader and trailer tape ..................................................42
Figure 52: PowerSSO-16 marking information .........................................................................................43
4/46 DocID027403 Rev 1

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VND7030AJ 전자부품, 판매, 대치품
VND7030AJ
Electrical specification
2 Electrical specification
Figure 3: Current and voltage conventions
IS
V
CC
I
FR
FaultRST
IOUT
I
SEn
OUTPUT0,1
SEn
ISENSE
VFn VCC
V
OUT
I
SEL
MultiSense
SEL0,1
V
SENSE
IIN
INPUT0,1
I
GND
GAPGCFT00315
VFn = VOUTn - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability.
Symbol
Table 3: Absolute maximum ratings
Parameter
Value Unit
VCC DC supply voltage
-VCC Reverse DC supply voltage
VCCPK
Maximum transient supply voltage (ISO 16750-2:2010 Test B clamped
to 40V; RL = 4 Ω)
VCCJS Maximum jump start voltage for single pulse short circuit protection
-IGND DC reverse ground pin current
IOUT OUTPUT0,1 DC output current
-IOUT
IIN
ISEn
ISEL
IFR
VFR
Reverse DC output current
INPUT0,1 DC input current
SEn DC input current
SEL0,1 DC input current
FaultRST DC input current
FaultRST DC input voltage
38
0.3
40
28
200
Internally
limited
29
-1 to 10
7.5
V
V
V
mA
A
mA
V
DocID027403 Rev 1
7/46

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VND7030AJ

Double channel high-side driver

STMicroelectronics
STMicroelectronics

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