PDF Si5322 Data sheet ( Hoja de datos )

Número de pieza	Si5322
Descripción	PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER
Fabricantes	Silicon Labs
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No Preview Available ! Si5322 PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER Features  Not recommended for new  Dual clock outputs with designs. For alternatives, see the selectable signal format: Si533x family of products. LVPECL, LVDS, CML, CMOS  Selectable output frequencies  Support for ITU G.709 FEC ratios ranging from 19.44 to 1050 MHz (255/238, 255/237, 255/236)  Low jitter clock outputs with jitter  LOS alarm output generation as low as 0.6 psRMS  Pin-programmable settings (50 kHz–80 MHz)  On-chip voltage regulator for  Integrated loop filter with 1.8 V ±5%, 2.5 or 3.3 V ±10% selectable loop bandwidth operation (150 kHz to 1.3 MHz)  Small size: 6 x 6 mm 36-lead  Dual clock inputs with manual or QFN automatically controlled switching  Pb-free, RoHS compliant Applications  SONET/SDH OC-48/STM-16  ITU G.709 line cards and OC-192/STM-64 line cards  Optical modules  GbE/10GbE, 1/2/4/8/10GFC line  Test and measurement cards Description The Si5322 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5322 accepts dual clock inputs ranging from 19.44 to 707 MHz and generates two equal frequency-multiplied clock outputs ranging from 19.44 to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates. The Si5322 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any- frequency synthesis in a highly-integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5322 is ideal for providing clock multiplication in high performance timing applications. Ordering Information: See page 18. Pin Assignments 36 35 34 33 32 31 30 29 28 RST 1 27 FRQSEL3 FRQTBL 2 26 FRQSEL2 C1B 3 25 FRQSEL1 C2B 4 VDD 5 GND 6 GND Pad 24 FRQSEL0 23 BWSEL1 22 BWSEL0 NC 7 21 CS_CA GND 8 20 GND AUTOSEL 9 19 GND 10 11 12 13 14 15 16 17 18 Rev. 1.0 9/14 Copyright © 2014 by Silicon Laboratories Si5322 1 page Si5322 Table 2. DC Characteristics (Continued) (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Unit Differential Input Voltage Swing VID fCKIN < 212.5 MHz 0.2 — — VPP See Figure 2. fCKIN > 212.5 MHz See Figure 2. 0.25 — — VPP Output Clocks (CKOUTn)1 Common Mode CKOVCM Differential Output Swing CKOVD Single-ended Output Swing CKOVSE Differential Output Voltage CKOVD Common Mode Output Voltage Differential Output Voltage CKOVCM CKOVD Common Mode Output Voltage Differential Output Resistance Output Voltage Low Output Voltage High CKOVCM CKORD CKOVOLLH CKOVOHLH LVPECL 100  load line-to-line LVPECL 100  load line-to-line LVPECL 100  load line-to-line CML 100  load line-to-line CML 100  load line-to-line LVDS 100  load line-to-line Low swing LVDS 100  load line-to-line LVDS 100  load line-to-line CML, LVDS, LVPECL VDD – 1.42 1.1 0.5 350 — 500 350 1.125 — — — — 425 VDD – 0.36 700 425 1.2 200 CMOS VDD = 1.71 V CMOS — 0.8 x VDD — — VDD – 1.25 1.9 0.93 500 — 900 500 1.275 — 0.4 — V VPP VPP mVPP V mVPP mVPP V  V V Output Drive Current CKOIO CMOS Driving into CKOVOL for out- put low or CKOVOH for output high. CKOUT+ and CKOUT– shorted externally. VDD = 1.8 V — 7.5 — mA VDD = 3.3 V — 32 — mA Notes: 1. LVPECL outputs require nominal VDD > 2.5 V. 2. No overshoot or undershoot. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most designs, an external resistor voltage divider is recommended. Rev. 1.0 5 5 Page Si5322 622 MHz In, 622 MHz Out BW=877 kHz -50 -70 -90 -110 -130 -150 -170 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Figure 5. Typical Phase Noise Plot Table 8. Typical Jitter Data Jitter Bandwidth OC-48, 12 kHz to 20 MHz OC-192, 20 kHz to 80 MHz OC-192, 4 MHz to 80 MHz RMS Jitter (fs) 374 388 181 OC-192, 50 kHz to 80 MHz Broadband, 800 Hz to 80 MHz 377 420 Rev. 1.0 11 11 Page

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