PDF Si5319 Data sheet ( Hoja de datos )

Número de pieza	Si5319
Descripción	ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Fabricantes	Silicon Laboratories
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Si5319 ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR Features  Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 2 kHz to 710 MHz  Ultra-low jitter clock output with jitter generation as low as 0.3 ps rms (50 kHz–80 MHz)  Integrated loop filter with selectable loop bandwidth (60 Hz to 8.4 kHz)  Meets OC-192 GR-253-CORE jitter specifications  Clock or crystal input with manual clock selection  Selectable clock output signal format (LVPECL, LVDS, CML, CMOS)  Support for ITU G.709 and custom OTN FEC ratios (e.g. 255/238, 255/237, 255/236)  Supports various frequency translations for Synchronous Ethernet  LOL, LOS alarm outputs  I2C or SPI programmable  On-chip voltage regulator for 1.8 V ±5%, 2.5 V ±10% or 3.3 V ±10% operation  Small size: 6 x 6 mm 36-lead QFN  Pb-free, ROHS compliant Applications  10G/40G/100G OTN line cards  SONET/SDH OC-48/STM-16 and OC-192/STM-64 line cards  GbE/10GbE, 1/2/4/8/10GFC line cards  ITU G.709 and custom FEC line cards  Synchronous Ethernet  Optical modules  Wireless basestations  Data converter clocking  DSLAM/MSANs  Test and measurement  Broadcast video  Discrete PLL replacement Description The Si5319 is a jitter-attenuating precision M/N clock multiplier for applications requiring sub 1 ps jitter performance. The Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The Si5319 can also use its crystal oscillator as a clock source for free-running clock generation. The device provides virtually any frequency translation combination across this operating range. The Si5319 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5319 is based on Silicon Laboratories' third-generation DSPLL® technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5319 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Rev. 1.0 12/10 Copyright © 2010 by Silicon Laboratories Si5319 1 page Si5319 Table 2. DC Characteristics (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Supply Current1 Symbol IDD Test Condition LVPECL Format 622.08 MHz Out Min Typ — 217 Max Unit 243 mA CMOS Format 19.44 MHz Out — 194 220 mA Disable Mode — 165 — mA CKIN Input Pin2 Input Common Mode Voltage (Input Thresh- old Voltage) VICM 1.8 V ± 5% 2.5 V ± 10% 0.9 — 1— 1.4 V 1.7 V 3.3 V ± 10% 1.1 — 1.95 V Input Resistance CKNRIN Single-ended 20 40 60 kΩ Single-Ended Input Voltage Swing (See Absolute Specs) VISE Differential Input Voltage Swing (See Absolute Specs) VID Output Clock (CKOUT)3 fCKIN < 212.5 MHz See Figure 1. fCKIN > 212.5 MHz See Figure 1. fCKIN < 212.5 MHz See Figure 1. fCKIN > 212.5 MHz See Figure 1. 0.2 0.25 0.2 0.25 — — — — — VPP — VPP — VPP — VPP Common Mode CKOVCM LVPECL 100  load VDD –1.42 line-to-line — VDD –1.25 V Differential Output Swing CKOVD LVPECL 100  load line-to-line 1.1 — 1.9 VPP Single Ended Output CKOVSE LVPECL 100  load 0.5 — 0.93 VPP Swing line-to-line Differential Output Voltage CKOVD CML 100  load line-to- line 350 425 500 mVPP Notes: 1. Current draw is independent of supply voltage. 2. No under- or overshoot is allowed. 3. LVPECL outputs require nominal VDD ≥ 2.5 V. 4. This is the amount of leakage that the 3-level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. Rev. 1.0 5 5 Page Si5319 Table 4. AC Specifications (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition LVCMOS Output Pins Min Rise/Fall Times LOSn Trigger Window Time to Clear LOL after LOS Cleared Device Skew tRF LOSTRIG tCLRLOL CLOAD = 20pf See Figure 2 From last CKINn to  Internal detection of LOSn N3 ≠ 1 LOS to LOL Fold = Fnew Stable Xa/XB reference — — — Input to Output Phase Change Due to Tem- perature Variation tTEMP Max phase changes from –40 to +85 °C PLL Performance (fin=fout = 622.08 MHz; BW=120 Hz; LVPECL) Lock Time tLOCKMP Start of ICAL to of LOL — — Output Clock Phase Change Closed Loop Jitter Peaking Jitter Tolerance Phase Noise fout = 622.08 MHz tP_STEP JPK JTOL CKOPN After clock switch f3  128 kHz — — Jitter Frequency Loop Bandwidth 1 kHz Offset 10 kHz Offset 100 kHz Offset 5000/BW — — — 1 MHz Offset — Subharmonic Noise Spurious Noise SPSUBH SPSPUR Phase Noise @ 100 kHz Offset Max spur @ n x F3 (n  1, n x F3 < 100 MHz) — — Typ 25 — 10 300 35 200 0.05 — –106 –121 –132 –132 –88 –93 Max Unit — ns 4.5 x N3 TCKIN — ms 500 ps 1200 — ms ps 0.1 dB — ns pk-pk –87 –100 –104 –119 –76 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc –70 dBc Rev. 1.0 11 11 Page

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