PDF Si5368 Data sheet ( Hoja de datos )

Número de pieza	Si5368
Descripción	ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Fabricantes	Silicon Labs
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Si5368 ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR Features  Generates any frequency from  Supports holdover and freerun 2 kHz to 945 MHz and select modes of operation frequencies to 1.4 GHz from an  Five clock outputs with input frequency of 2 kHz to selectable signal format 710 MHz (LVPECL, LVDS, CML, CMOS)  Ultra-low jitter clock outputs with  SONET frame sync switching jitter generation as low as 300 fs and regeneration rms (12 kHz–20 MHz)  Support for ITU G.709 and  Integrated loop filter with selectable custom FEC ratios (253/226, loop bandwidth (60 Hz to 8.4 kHz) 239/237, 255/238, 255/237,  Meets OC-192 GR-253-CORE jitter 255/236) specifications  LOL, LOS, FOS alarm outputs  Four clock inputs with manual or  Digitally-controlled output phase automatically controlled hitless adjust switching and phase build-out  Small size: 14 x 14 mm 100-pin TQFP  I2C or SPI programmable settings  Pb-free, RoHS compliant Applications  SONET/SDH OC-48/STM-16/OC- Data converter clocking 192/STM-64 line cards  OTN/WDM Muxponder, MSPP,  GbE/10GbE, 1/2/4/8/10/16G Fibre ROADM line cards Channel  SONET/SDH + PDH clock  ITU G.709 and custom FEC line synthesis cards  Test and measurement  Wireless basestations  Synchronous Ethernet  Broadcast video Description The Si5368 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter performance. The Si5368 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range. The outputs are divided down separately from a common sporougrcraem. TmhaebSlei5t3h6ro8uignhpuatncloI2cCk frequency and clock multiplication ratio or SPI interface. The Si5368 is based are on Silicon Laboratories' third-generation DSPLL® technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5 ,or 3.3 V supply, the Si5368 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Ordering Information: See page 79. Pin Assignments NC NC RST NC VDD VDD GND GND C1B C2B C3B T_ALM 0_C3A GND VDD XA XB GND GND NC ALIGN NC NC NC NC 100 99 1 2 3 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 Si536812 64 13 63 14 62 15 61 16 60 17 59 18 19 GND PAD 58 57 20 56 21 55 22 54 23 53 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 52 51 49 50 NC NC NC NC SDI A2_SS A1 A0 NC NC GND GND VDD VDD SDA_SDO SCL C2A C1A CS1_C4A NC INC DEC NC NC NC Rev. 1.0 8/12 Copyright © 2012 by Silicon Laboratories Si5368 1 page Si5368 Table 2. DC Characteristics (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit CKINn Input Pins2 Input Common Mode Voltage (Input Thresh- old Voltage) VICM 1.8 V ± 5% 2.5 V ± 10% 0.9 — 1.4 V 1 — 1.7 V 3.3 V ± 10% 1.1 — 1.95 V Input Resistance CKNRIN Single-ended 20 40 60 k Single-Ended Input Voltage Swing (See Absolute Specs) Differential Input Voltage Swing (See Absolute Specs) VISE VID fCKIN < 212.5 MHz See Figure 1. fCKIN > 212.5 MHz See Figure 1. fCKIN < 212.5 MHz See Figure 1. fCKIN > 212.5 MHz See Figure 1. 0.2 0.25 0.2 0.25 — — — — — VPP — VPP — VPP — VPP Output Clocks (CKOUTn)3,5,6 Common Mode CKOVCM Differential Output Swing Single Ended Output Swing Differential Output Volt- age Common Mode Output Voltage CKOVD CKOVSE CKOVD CKOVCM LVPECL 100  load line-to-line LVPECL 100  load line-to-line LVPECL 100  load line-to-line CML 100  load line- to-line CML 100  load line- to-line VDD –1.42 1.1 0.5 350 — — — — 425 VDD-0.36 VDD –1.25 1.9 0.93 500 — V VPP VPP mVPP V Notes: 1. Current draw is independent of supply voltage 2. No under- or overshoot is allowed. 3. LVPECL outputs require nominal VDD ≥ 2.5 V. 4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. 6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled. When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS. Rev. 1.0 5 5 Page Table 3. AC Specifications (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Device Skew Symbol Test Condition Min Output Clock Skew tSKEW  of CKOUTn to  of CKOUT_m, CKOUTn and CKOUT_m at same frequency and signal format PHASEOFFSET = 0 CKOUT_ALWAYS_ON = 1 SQ_ICAL = 1 Phase Change due to Temperature Variation* tTEMP Max phase changes from –40 to +85 °C PLL Performance (fin = fout = 622.08 MHz; BW = 120 Hz; LVPECL) Lock Time tLOCKMP Start of ICAL to of LOL — — — Output Clock Phase Change Closed Loop Jitter Peaking Jitter Tolerance Phase Noise fout = 622.08 MHz tP_STEP JPK JTOL After clock switch f3  128 kHz — — Jitter Frequency Loop Bandwidth 1 kHz Offset 5000/BW — Typ — 300 35 200 0.05 — –106 CKOPN 10 kHz Offset 100 kHz Offset — –121 — –132 1 MHz Offset — –132 Spurious Noise SPSPUR Max spur @ n x F3 (n  1, n x F3 < 100 MHz) — –93 *Note: Input to output phase skew after an ICAL is not controlled and can assume any value. Si5368 Max Unit 100 ps 500 ps 1200 — ms ps 0.1 dB — ns pk-pk — dBc/Hz — dBc/Hz — dBc/Hz — dBc/Hz –70 dBc Rev. 1.0 11 11 Page

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