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PDF LPC12D27 Data sheet ( Hoja de datos )
| Número de pieza | LPC12D27 | |
| Descripción | 32-bit ARM Cortex-M0 microcontroller | |
| Fabricantes | NXP Semiconductors | |
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LPC12D27
32-bit ARM Cortex-M0 microcontroller; 128 kB flash and 8 kB
SRAM; 40 segment x 4 LCD driver
Rev. 1 — 20 September 2011
Product data sheet
1. General description
The LPC12D27 are ARM Cortex-M0 based microcontrollers for embedded applications
featuring a high level of integration and low power consumption. The ARM Cortex-M0 is a
next generation core that offers system enhancements such as enhanced debug features
and a higher level of support block integration.
The LPC12D27 is a dual-chip module consisting of a LPC1227 single-chip microcontroller
combined with a PCF8576D Universal LCD driver in a low-cost 100-pin package. The
LCD driver provides 40 segments and supports from one to four backplanes. Display
overhead is minimized by an on-chip display RAM with auto-increment addressing.
The LPC12D27 operate at CPU frequencies of up to 45 MHz and include 128 kB of flash
memory and 8 kB of data memory.
The peripheral complement of the LPC1227 microcontroller includes a micro DMA
controller, one Fast-mode Plus I2C interface, one SSP interface, two UARTs, four general
purpose timers, a 10-bit ADC, two comparators, and up to 40 general purpose I/O pins.
Remark: For a functional description of the LPC1227 microcontroller see the LPC122x
data sheet. For a detailed description of the LCD driver see the PCF8576D data sheet.
Both data sheets are available at http://www.nxp.com/microcontrollers
2. Features and benefits
LCD driver
40 segments.
One to four backplanes.
On-chip display RAM with auto-increment addressing.
Processor core
ARM Cortex-M0 processor, running at frequencies of up to 45 MHz (one wait state
from flash) or 30 MHz (zero wait states from flash). The LPC12D27 have a high
score of over 45 in CoreMark CPU performance benchmark testing, equivalent to
1.51/MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Serial Wire Debug (SWD).
System tick timer.
Memory
8 kB SRAM.
128 kB on-chip flash programming memory.
1 page  
NXP Semiconductors
LPC12D27
32-bit ARM Cortex-M0 microcontroller
GPIO ports
SWD
LPC1227
TEST/DEBUG
INTERFACE
ARM
CORTEX-M0
system
bus
HIGH-SPEED
GPIO
XTALIN
XTALOUT
RESET
clocks and
controls
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
MICRO DMA
CONTROLLER
128 kB
FLASH
8 kB
SRAM
ROM
master
slave
slave
AHB-LITE BUS
slave
AHB-ABB
BRIDGE
CRC
ENGINE
slave
CLKOUT
SCK
SSEL
MISO
MOSI
RXD0
TXD0
DTR0, DSR0, CTS0,
DCD0, RI0, RTS0
RXD1
TXD1
SCL
SDA
4 x MAT
4 x CAP
2 x MAT
2 x CAP
SSP/SPI
UART0 RS-485
UART1
I2C-bus
32-bit COUNTER/TIMER 0/1
16-bit COUNTER/TIMER 0/1
Fig 2. LPC12D27 block diagram (microcontroller)
10-bit ADC
COMPARATOR0/1
AD[7:0]
ACMP0/1_I[3:0]
ACMP0/1_O
VREF_CMP
WINDOWED WDT
IOCONFIG
REAL-TIME CLOCK
SYSTEM CONTROL
MICRO DMA REGISTERS
RTCXOUT
RTCXIN
002aag501
LPC12D27
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 September 2011
© NXP B.V. 2011. All rights reserved.
5 of 46
5 Page 
NXP Semiconductors
LPC12D27
32-bit ARM Cortex-M0 microcontroller
Table 3. LPC12D27 LQFP100 pin description …continued
Symbol
Pin Start Reset Type Description
logic state
input [1]
SWDIO/ACMP1_I2/
CT32B1_CAP2/
CT32B1_MAT2/PIO0_25
1[5]
no
I; PU
I/O
I
I
SWDIO — Serial wire debug input/output, default location.
ACMP1_I2 — Input 2 for comparator 1.
CT32B1_CAP2 — Capture input, channel 2 for 32-bit timer 1.
O CT32B1_MAT2 — Match output, channel 2 for 32-bit timer 1.
I/O PIO0_25 — General purpose digital input/output pin.
SWCLK/
ACMP1_I3/
CT32B1_CAP3/
CT32B1_MAT3/PIO0_26
2[5]
no
I; PU
I
I
I
O
SWCLK — Serial wire clock, default location.
ACMP1_I3 — Input 3 for comparator 1.
CT32B1_CAP3 — Capture input, channel 3 or 32-bit timer 1.
CT32B1_MAT3 — Match output, channel 3 for 32-bit timer 1.
I/O PIO0_26 — General purpose digital input/output pin.
PIO0_27/ACMP0_O
3[7] no
I; PU I/O
PIO0_27 — General purpose digital input/output pin
(high-current output driver).
O ACMP0_O — Output for comparator 0.
PIO0_28/ACMP1_O/
CT16B0_CAP0/
CT16B0_MAT0
4[7] no
I; PU I/O
O
PIO0_28 — General purpose digital input/output pin
(high-current output driver).
ACMPC1_O — Output for comparator 1.
I CT16B0_CAP0 — Capture input, channel 0 for 16-bit timer 0.
O CT16B0_MAT0 — Match output, channel 0 for 16-bit timer 0.
PIO0_29/ROSC/
CT16B0_CAP1/
CT16B0_MAT1
5[7] no
I; PU I/O
I/O
PIO0_29 — General purpose digital input/output pin
(high-current output driver).
ROSC — Relaxation oscillator for 555 timer applications.
I CT16B0_CAP1 — Capture input, channel 1 for 16-bit timer 0.
O CT16B0_MAT1 — Match output, channel 1 for 16-bit timer 0.
R/PIO0_30/AD0
26[5] no I; PU I
R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O PIO0_30 — General purpose digital input/output pin.
I AD0 — A/D converter, input 0.
R/PIO0_31/AD1
27[5] no I; PU I
R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O PIO0_31 — General purpose digital input/output pin.
I AD1 — A/D converter, input 1.
PIO1_0 to PIO1_6
I/O Port 1 — Port 1 is a 32-bit I/O port with individual direction and
function controls for each bit. The operation of port 1 pins
depends on the function selected through the IOCONFIG register
block. Pins PIO1_7 through PIO1_31 are not available.
R/PIO1_0/AD2
28[5] no I; PU O
R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O PIO1_0 — General purpose digital input/output pin.
I AD2 — A/D converter, input 2.
LPC12D27
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 September 2011
© NXP B.V. 2011. All rights reserved.
11 of 46
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