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AD5172 PDF 데이터시트 ( Data , Function )

부품번호 AD5172 기능
기능 Dual-Channel I2C Digital Potentiometers
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AD5172 데이터시트, 핀배열, 회로
Data Sheet
256-Position, One-Time Programmable,
Dual-Channel, I2C Digital Potentiometers
AD5172/AD5173
FEATURES
2-channel, 256-position potentiometers
One-time programmable (OTP) set-and-forget resistance
setting provides a low cost alternative to EEMEM
Unlimited adjustments prior to OTP activation
OTP overwrite allows dynamic adjustments with user-
defined preset
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ
Compact 10-lead MSOP: 3 mm × 4.9 mm
Fast settling time: tS = 5 μs typical on power-up
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins: AD0 and AD1 (AD5173 )
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power: IDD = 6 μA maximum
Wide operating temperature: −40°C to +125°C
FUNCTIONAL BLOCK DIAGRAMS
A1 W1 B1
A2 W2 B2
VDD
GND
FUSE
LINKS
12
RDAC
REGISTER 1
RDAC
REGISTER 2
SDA
SCL
/8
SERIAL INPUT
REGISTER
Figure 1. AD5172 Functional Block Diagram
W1 B1
W2 B2
APPLICATIONS
Systems calibration
Electronics level setting
Mechanical trimmers replacement in new designs
Permanent factory PCB setting
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
GENERAL DESCRIPTION
The AD5172/AD5173 are dual-channel, 256-position, one-time
programmable (OTP) digital potentiometers1 that employ fuse
link technology to achieve memory retention of resistance
settings. OTP is a cost-effective alternative to EEMEM for users
who do not need to program the digital potentiometer setting
in memory more than once. These devices perform the same
electronic adjustment function as mechanical potentiometers or
variable resistors but with enhanced resolution, solid-state reliabil-
ity, and superior low temperature coefficient performance.
The AD5172/AD5173 are programmed using a 2-wire, I2C®-
compatible digital interface. Unlimited adjustments are allowed
VDD
GND
FUSE
LINKS
12
RDAC
REGISTER 1
RDAC
REGISTER 2
AD0 ADDRESS
/AD1
DECODE
8
SDA
SCL
SERIAL INPUT
REGISTER
Figure 2. AD5173 Functional Block Diagram
before permanently setting the resistance value. During OTP
activation, a permanent blow fuse command freezes the wiper
position (analogous to placing epoxy on a mechanical trimmer).
Unlike traditional OTP digital potentiometers, the AD5172/
AD5173 have a unique temporary OTP overwrite feature that
allows for new adjustments even after a fuse is blown. However,
the OTP setting is restored during subsequent power-up condi-
tions. This allows users to treat these digital potentiometers as
volatile potentiometers with a programmable preset.
1 The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. I
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD5172 pdf, 반도체, 판매, 대치품
AD5172/AD5173
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS: 2.5 kΩ
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
DC CHARACTERISTICS—POTENTIOMETER DIVIDER
MODE4
Differential Nonlinearity5
Integral Nonlinearity5
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range6
Capacitance A, B7
Capacitance W7
Shutdown Supply Current8
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
SDA and SCL
Input Logic High9
Input Logic Low9
AD0 and AD1
Input Logic High
Input Logic Low
Input Current
Input Capacitance7
POWER SUPPLIES
Power Supply Range
OTP Supply Voltage9, 10
Supply Current
OTP Supply Current9, 11, 12
Power Dissipation13
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS14
Bandwidth, −3 dB
Total Harmonic Distortion
Symbol
R-DNL
R-INL
∆RAB
(∆RAB/RAB)/∆T
RWB
DNL
INL
(ΔVW/VW)/ΔT
VWFSE
VWZSE
VA, VB, VW
CA, CB
CW
IA_SD
ICM
VIH
VIL
VIH
VIL
IIL
CIL
VDD_RANGE
VDD_OTP
IDD
IDD_OTP
PDISS
PSS
BW
THDW
Conditions
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
Code = 0x00, VDD = 5 V
Code = 0x80
Code = 0xFF
Code = 0x00
f = 1 MHz, measured to
GND, code = 0x80
f = 1 MHz, measured to
GND, code = 0x80
VDD = 5.5 V
VA = VB = VDD/2
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
VIN = 0 V or 5 V
TA = 25°C
VIH = 5 V or VIL = 0 V
VDD_OTP = 5.0 V, TA = 25°C
VIH = 5 V or VIL = 0 V, VDD = 5 V
VDD = 5 V ± 10%,
code = midscale
Code = 0x80
VA = 1 V rms, VB = 0 V,
f = 1 kHz
Min
−2
−14
−20
−1.5
−2
−14
0
GND
0.7 VDD
−0.5
2.1
2.7
5.6
Typ 1
±0.1
±2
35
160
±0.1
±0.6
15
−5.5
4.5
45
60
0.01
1
5
5.7
3.5
100
±0.02
4.8
0.1
Max
+2
+14
+55
200
+1.5
+2
0
12
VDD
1
VDD + 0.5
+0.3 VDD
0.6
±1
5.5
5.8
6
33
±0.08
Unit
LSB
LSB
%
ppm/°C
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
µA
nA
V
V
V
V
µA
pF
V
V
µA
mA
µW
%/%
MHz
%
Rev. I | Page 4 of 28

4페이지










AD5172 전자부품, 판매, 대치품
Data Sheet
TIMING CHARACTERISTICS
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter
I2C INTERFACE TIMING CHARACTERISTICS1
SCL Clock Frequency
Bus-Free Time Between Stop and Start, tBUF
Hold Time (Repeated Start), tHD;STA
Low Period of SCL Clock, tLOW
High Period of SCL Clock, tHIGH
Setup Time for Repeated Start Condition, tSU;STA
Data Hold Time, tHD;DAT2
Data Setup Time, tSU;DAT
Fall Time of Both SDA and SCL Signals, tF
Rise Time of Both SDA and SCL Signals, tR
Setup Time for Stop Condition, tSU;STO
OTP Program Time
Symbol Conditions
fSCL
t1
t2 After this period, the first clock
pulse is generated.
t3
t4
t5
t6
t7
t8
t9
t10
t11
1 See the timing diagrams for the locations of measured values (that is, see Figure 3 and Figure 48 to Figure 51).
2 The maximum tHD;DAT has to be met only if the device does not stretch the low period (tLOW) of the SCL signal.
Timing Diagram
SCL
t2
SDA
t1
PS
t8 t6 t9
t3
t8 t9
t4
t7
t2
t5
S
Figure 3. I2C Interface Detailed Timing Diagram
AD5172/AD5173
Min Typ Max Unit
400 kHz
1.3 μs
0.6 μs
1.3 μs
0.6 μs
0.6 μs
0.9 μs
100 ns
300 ns
300 ns
0.6 μs
400 ms
t10
P
Rev. I | Page 7 of 28

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