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ADF4111 PDF 데이터시트 ( Data , Function )

부품번호 ADF4111 기능
기능 RF PLL Frequency Synthesizers
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ADF4111 데이터시트, 핀배열, 회로
Data Sheet
RF PLL Frequency Synthesizers
ADF4110/ADF4111/ADF4112/ADF4113
FEATURES
GENERAL DESCRIPTION
ADF4110: 550 MHz; ADF4111: 1.2 GHz; ADF4112: 3.0 GHz;
ADF4113: 4.0 GHz
2.7 V to 5.5 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems
Programmable dual-modulus prescaler 8/9, 16/17, 32/33,
64/65
The ADF4110 family of frequency synthesizers can be used to
implement local oscillators in the upconversion and downcon-
version sections of wireless receivers and transmitters. They
consist of a low noise digital PFD (phase frequency detector), a
precision charge pump, a programmable reference divider,
programmable A and B counters, and a dual-modulus prescaler
Programmable charge pump currents
(P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction
Programmable antibacklash pulse width
with the dual-modulus prescaler (P/P + 1), implement an N
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
divider (N = BP + A). In addition, the 14-bit reference counter
(R counter) allows selectable REFIN frequencies at the PFD
input. A complete phase-locked loop (PLL) can be implemented
APPLICATIONS
Base stations for wireless radio (GSM, PCS, DCS, CDMA,
if the synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO).
WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications test equipment
Control of all the on-chip registers is via a simple 3-wire
interface. The devices operate with a power supply ranging
from 2.7 V to 5.5 V and can be powered down when not in use.
CATV equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP CPGND
RSET
REFERENCE
REFIN
CLK
DATA
LE
RFINA
RFINB
24-BIT
INPUT REGISTER 22
SDOUT
14-BIT
R COUNTER
14
R COUNTER
LATCH
FUNCTION
LATCH
A, B COUNTER
LATCH
19
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
LOCK
DETECT
CURRENT CURRENT
SETTING 1 SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
FROM
FUNCTION
LATCH
13
N = BP + A
13-BIT
B COUNTER
PRESCALER
P/P +1
LOAD
LOAD
6-BIT
A COUNTER
AVDD
SDOUT
MUX
HIGH Z
M3 M2 M1
ADF4110/ADF4111
6 ADF4112/ADF4113
CE
AGND
DGND
Figure 1. Functional Block Diagram
CP
MUXOUT
Rev. F
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ADF4111 pdf, 반도체, 판매, 대치품
ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
Parameter
POWER SUPPLIES
AVDD
DVDD
VP
IDD5 (AIDD + DIDD)
ADF4110
ADF4111
ADF4112
ADF4113
IP
Low Power Sleep Mode
NOISE CHARACTERISTICS
ADF4113 Normalized Phase Noise Floor6
Phase Noise Performance7
ADF4110: 540 MHz Output8
ADF4111: 900 MHz Output9
ADF4112: 900 MHz Output9
ADF4113: 900 MHz Output9
ADF4111: 836 MHz Output10
ADF4112: 1750 MHz Output11
ADF4112: 1750 MHz Output12
ADF4112: 1960 MHz Output13
ADF4113: 1960 MHz Output13
ADF4113: 3100 MHz Output14
Spurious Signals
ADF4110: 540 MHz Output9
ADF4111: 900 MHz Output9
ADF4112: 900 MHz Output9
ADF4113: 900 MHz Output9
ADF4111: 836 MHz Output10
ADF4112: 1750 MHz Output11
ADF4112: 1750 MHz Output12
ADF4112: 1960 MHz Output13
ADF4113: 1960 MHz Output13
ADF4113: 3100 MHz Output14
B Version B Chips1 Unit
2.7/5.5
AVDD
AVDD/6.0
2.7/5.5
AVDD
AVDD/6.0
V min/V max
V min/V max
5.5 4.5 mA max
5.5 4.5 mA max
7.5 6.5 mA max
11 8.5 mA max
0.5 0.5 mA max
1 1 µA typ
−215
−215
dBc/Hz typ
−91 −91 dBc/Hz typ
−87 −87 dBc/Hz typ
−90 −90 dBc/Hz typ
−91 −91 dBc/Hz typ
−78 −78 dBc/Hz typ
−86 −86 dBc/Hz typ
−66 −66 dBc/Hz typ
−84 −84 dBc/Hz typ
−85 −85 dBc/Hz typ
−86 −86 dBc/Hz typ
−97/−106
−98/−110
−91/−100
−100/−110
−81/−84
−88/−90
−65/−73
−80/−84
−80/−84
−80/−82
−97/−106
−98/−110
−91/−100
−100/−110
−81/−84
−88/−90
−65/−73
−80/−84
−80/−84
−82/−82
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
Test Conditions/Comments
AVDD ≤ VP ≤ 6.0 V. See Figure 25 and Figure 26.
4.5 mA typical.
4.5 mA typical.
6.5 mA typical.
8.5 mA typical.
TA = 25°C.
@ VCO output.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 300 Hz offset and 30 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 200 Hz offset and 10 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 1 MHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 30 kHz/60 kHz and 30 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 10 kHz/20 kHz and 10 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 1 MHz/2 MHz and 1 MHz PFD frequency.
1The B chip specifications are given as typical values.
2This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
3AC coupling ensures AVDD/2 bias. See Figure 33 for a typical circuit.
4Guaranteed by design.
5 TA = 25°C; AVDD = DVDD = 3 V; P = 16; SYNC = 0; DLY = 0; RFIN for ADF4110 = 540 MHz; RFIN for ADF4111, ADF4112, ADF4113 = 900 MHz.
6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider
value) and 10logFPFD: PNSYNTH = PNTOT – 10logFPFD – 20logN.
7 The phase noise is measured with the EV-ADF411XSD1Z evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the
synthesizer (fREFOUT = 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (Table 7).
8 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; loop B/W = 20 kHz.
9 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop B/W = 20 kHz.
10 fREFIN = 10 MHz; fPFD = 30 kHz; offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; loop B/W = 3 kHz.
11 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; loop B/W = 20 kHz
12 fREFIN = 10 MHz; fPFD = 10 kHz; offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; loop B/W = 1 kHz.
13 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; loop B/W = 20 kHz.
14 fREFIN = 10 MHz; fPFD = 1 MHz; offset frequency = 1 kHz; fRF = 3100 MHz; N = 3100; loop B/W = 20 kHz.
Rev. F | Page 4 of 28

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ADF4111 전자부품, 판매, 대치품
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RSET 1
16 VP
CP 2 ADF4110 15 DVDD
CPGND 3 ADF4111 14 MUXOUT
AGND 4 ADF4112 13 LE
ADF4113
RFINB 5
12 DATA
RFINA 6 TOP VIEW 11 CLK
AVDD 7 (Not to Scale) 10 CE
REFIN 8
9 DGND
Figure 3. TSSOP Pin Configuration
CPGND 1
AGND 2
AGND 3
RFINB 4
RFINA 5
ADF4110
ADF4111
ADF4112
ADF4113
TOP VIEW
(Not to Scale)
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
NOTES
1. THE EXPOSED PADDLE SHOULD BE CONNECTED TO AGND.
Figure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
TSSOP
Pin No.
LFCSP
Pin No. Mnemonic
1 19 RSET
2 20 CP
3 1 CPGND
4 2, 3 AGND
5 4 RFINB
6 5 RFINA
7 6, 7 AVDD
8 8 REFIN
9 9, 10 DGND
10 11 CE
11 12 CLK
12 13 DATA
13 14 LE
14 15 MUXOUT
15
16, 17
DVDD
16 18 VP
EPAD
Function
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the RSET pin is 0.56 V. The relationship between ICP and RSET is
I CPmax
=
23.5
RSET
So, with RSET = 4.7 kΩ, ICPmax = 5 mA.
Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn
drives the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF. See Figure 29.
Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO.
Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2, and an equivalent input
resistance of 100 kΩ. See Figure 28. This input can be driven from a TTL or CMOS crystal oscillator, or
can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into
three-state mode. Taking the pin high powers up the device depending on the status of the power-
down Bit F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS
input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches; the latch is selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
VP can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V. 1
Exposed Pad (LFCSP Only). The exposed paddle should be connected to AGND.
Rev. F | Page 7 of 28

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