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ADF4107 PDF 데이터시트 ( Data , Function )

부품번호 ADF4107 기능
기능 PLL Frequency Synthesizer
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ADF4107 데이터시트, 핀배열, 회로
Data Sheet
PLL Frequency Synthesizer
ADF4107
FEATURES
7.0 GHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems
Programmable dual-modulus prescaler
8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
APPLICATIONS
Broadband wireless access
Satellite systems
Instrumentation
Wireless LANs
Base stations for wireless radio
GENERAL DESCRIPTION
The ADF4107 frequency synthesizer can be used to implement
local oscillators in the upconversion and downconversion sections
of wireless receivers and transmitters. It consists of a low noise
digital PFD (phase frequency detector), a precision charge pump, a
programmable reference divider, programmable A and B counters,
and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B
(13-bit) counters, in conjunction with the dual-modulus
prescaler (P/P + 1), implement an N divider (N = BP + A). In
addition, the 14-bit reference counter (R counter), allows
selectable REFIN frequencies at the PFD input. A complete PLL
(phase-locked loop) can be implemented if the synthesizer is
used with an external loop filter and VCO (voltage controlled
oscillator). Its very high bandwidth means that frequency
doublers can be eliminated in many high frequency systems,
simplifying system architecture and reducing cost.
AVDD DVDD
FUNCTIONAL BLOCK DIAGRAM
VP CPGND
RSET
REFERENCE
REFIN
CLK
DATA
LE
RFINA
RFINB
14-BIT
R COUNTER
14
R COUNTER
LATCH
24-BIT INPUT
REGISTER 22
FUNCTION
LATCH
SDOUT
FROM
FUNCTION
LATCH
A, B COUNTER
LATCH
13
N = BP + A
13-BIT
B COUNTER
PRESCALER
P/P + 1
LOAD
LOAD
6-BIT
A COUNTER
CE AGND DGND
6
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
LOCK
DETECT
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
HIGH Z
19 AVDD
MUX
MUXOUT
SDOUT
M3 M2 M1
ADF4107
Figure 1.
Rev. D
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADF4107 pdf, 반도체, 판매, 대치품
Data Sheet
ADF4107
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN,
unless otherwise noted.
Table 1.
Parameter
RF CHARACTERISTICS
RF Input Frequency (RFIN)3
RF Input Sensitivity
Maximum Allowable Prescaler Output
Frequency4
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity5
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency7
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
B Version1
1.0/7.0
–5/+5
300
20/250
0.8/VDD
10
±100
104
5
625
2.5
3.0 to 11
1
2
1.5
2
1.4
0.6
±1
10
1.4
VOH, Output High Voltage
IOH
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
VP
IDD8 (AIDD + DIDD)
IP
Power-Down Mode9 (AIDD + DIDD)
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PNSYNTH)10
VDD − 0.4
100
0.4
2.7/3.3
AVDD
AVDD/5.5
17
0.4
10
−223
Normalized 1/f Noise (PN1_f)11
−122
B Chips2 (Typ) Unit
Test Conditions/Comments
1.0/7.0
–5/+5
300
GHz min/max
dBm min/max
MHz max
See Figure 18 for input circuit
20/250
0.8/VDD
10
±100
104
5
625
2.5
3.0 to 11
1
2
1.5
2
1.4
0.6
±1
10
1.4
VDD − 0.4
100
0.4
2.7/3.3
AVDD
AVDD/5.5
15
0.4
10
−223
−122
MHz min/max
V p-p min/max
pF max
µA max
For f < 20 MHz, ensure slew rate >50 V/µs
Biased at AVDD/26
MHz max
ABP = 0,0 (2.9 ns antibacklash pulse width)
Programmable; see Figure 25
mA typ
µA typ
% typ
kΩ typ
nA typ
% typ
% typ
% typ
With RSET = 5.1 kΩ
With RSET = 5.1 kΩ
See Figure 25
0.5 V ≤ VCP ≤ VP − 0.5 V
0.5 V ≤ VCP ≤ VP − 0.5 V
VCP = VP/2
V min
V max
µA max
pF max
V min
V min
µA max
V max
Open-drain output chosen; 1 kΩ pull-up
resistor to 1.8 V
CMOS output chosen
IOL = 500 µA
V min/V max
V min/V max
mA max
mA max
µA typ
AVDD ≤ VP ≤ 5.5 V
15 mA typ
TA = 25°C
dBc/Hz typ
dBc/Hz typ
PLL loop BW = 500 kHz, measured at
100 kHz offset
10 kHz offset; normalized to 1 GHz
Rev. D | Page 3 of 20

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ADF4107 전자부품, 판매, 대치품
ADF4107
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Data Sheet
RSET 1
16 VP
CP 2
15 DVDD
CPGND 3 ADF4107 14 MUXOUT
AGND 4 TOP VIEW 13 LE
(Not to Scale)
RFINB 5
12 DATA
RFINA 6
11 CLK
AVDD 7
10 CE
REFIN 8
9 DGND
NOTES:
1. TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
Figure 3. Pin Configuration, TSSOP
CPGND 1
AGND 2
AGND 3
RFINB 4
RFINA 5
ADF4107
TOP VIEW
(Not to Scale)
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
NOTES
1. TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
2. THE EXPOSED PAD MUST BE
CONNECTED TO AGND.
Figure 4. Pin Configuration, LFCSP
Table 4. Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 19 RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
I CP MAX
=
25.5
RSET
so, with RSET = 5.1 kΩ, ICP MAX = 5 mA.
2 20 CP
Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which in turn drives
the external VCO.
3
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
4
2, 3 AGND
Analog Ground. This is the ground return path of the prescaler.
5 4 RFINB
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF. See Figure 18.
6 5 RFINA Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
7 6, 7 AVDD
Analog Power Supply. This voltage may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog
ground plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
8 8 REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input
resistance of 100 kΩ. See Figure 17. This input can be driven from a TTL or CMOS crystal oscillator or it can
be ac-coupled.
9
9, 10 DGND
Digital Ground.
10 11 CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode. Taking the pin high powers up the device, depending on the status of the power-down bit, F2.
11 12 CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 13 DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
13 14 LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches, the latch being selected using the control bits.
14 15 MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to
be accessed externally.
15 16, 17 DVDD
Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
16 18 VP
Charge Pump Power Supply. This voltage should be greater than or equal to VDD. In systems where VDD is 3 V, it
can be set to 5 V and used to drive a VCO with a tuning range of up to 5 V.
EP Exposed Pad. The exposed pad must be connected to AGND.
Rev. D | Page 6 of 20

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