Datasheet.kr   

ADF4116 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADF4116은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 ADF4116 자료 제공

부품번호 ADF4116 기능
기능 RF PLL Frequency Synthesizers
제조업체 Analog Devices
로고 Analog Devices 로고


ADF4116 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 28 페이지수

미리보기를 사용할 수 없습니다

ADF4116 데이터시트, 핀배열, 회로
RF PLL Frequency Synthesizers
ADF4116/ADF4117/ADF4118
FEATURES
GENERAL DESCRIPTION
ADF4116: 550 MHz
ADF4117: 1.2 GHz
ADF4118: 3.0 GHz
2.7 V to 5.5 V power supply
Separate VP allows extended tuning voltage in 3 V systems
Y Grade: −40°C to +125°C
Dual-modulus prescaler
ADF4116: 8/9
ADF4117/ADF4118: 32/33
3-wire serial interface
Digital lock detect
Power-down mode
Fastlock mode
The ADF411x family of frequency synthesizers can be used to
implement local oscillators (LO) in the upconversion and
downconversion sections of wireless receivers and transmitters.
They consist of a low noise digital phase frequency detector
(PFD), a precision charge pump, a programmable reference
divider, programmable A and B counters, and a dual-modulus
prescaler (P/P + 1). The A (5-bit) and B (13-bit) counters, in
conjunction with the dual-modulus prescaler (P/P + 1),
implement an N divider (N = BP + A). In addition, the 14-bit
reference counter (R counter) allows selectable REFIN frequencies
at the PFD input. A complete phase-locked loop (PLL) can be
implemented if the synthesizer is used with an external loop
filter and voltage controlled oscillator (VCO).
APPLICATIONS
All of the on-chip registers are controlled via a simple 3-wire
Base stations for wireless radio
(GSM, PCS, DCS, CDMA, WCDMA)
interface. The devices operate with a power supply ranging
from 2.7 V to 5.5 V and can be powered down when not in use.
Wireless handsets
(GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs
Communications test equipment
CATV equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP CPGND
ADF4116/ADF4117/ADF4118
REFERENCE
REFIN
CLK
DATA
LE
RFINA
RFINB
14-BIT
R COUNTER
14
R COUNTER
LATCH
21-BIT
INPUT REGISTER 19
FUNCTION
LATCH
SDOUT
FROM
FUNCTION LATCH
A, B COUNTER
LATCH
13
N = BP + A
13-BIT
B COUNTER
PRESCALER
P/P + 1
LOAD
LOAD
5-BIT
A COUNTER
18
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
AVDD
SDOUT
5
CE
AGND
DGND
Figure 1.
CHARGE
PUMP
MUX
HIGH Z
M3 M2 M1
FLO
SWITCH
CP
MUXOUT
FLO
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000–2007 Analog Devices, Inc. All rights reserved.




ADF4116 pdf, 반도체, 판매, 대치품
ADF4116/ADF4117/ADF4118
Parameter
POWER SUPPLIES
AVDD
DVDD
VP
IDD (AIDD + DIDD)6
ADF4116
ADF4117
ADF4118
IP
Low-Power Sleep Mode
NOISE CHARACTERISTICS
ADF4118 Normalized Phase Noise
Floor 7
Phase Noise Performance8
ADF4116 540 MHz Output9
ADF4117 900 MHz Output10
ADF4118 900 MHz Output10
ADF4117 836 MHz Output11
ADF4118 1750 MHz Output12
ADF4118 1750 MHz Output13
ADF4118 1960 MHz Output14
Spurious Signals
ADF4116 540 MHz Output10
ADF4117 900 MHz Output10
ADF4118 900 MHz Output 10
ADF4117 836 MHz Output11
ADF4118 1750 MHz Output12
ADF4118 1750 MHz Output13
ADF4118 1960 MHz Output14
B Version1 Y Version2 Unit
2.7 to 5.5
AVDD
AVDD to 6.0
2.7 to 5.5
AVDD
AVDD to 6.0
V min to V max
V min to V max
5.5 mA max
5.5 mA max
7.5 7.5 mA max
0.4 0.4 mA max
1 1 μA typ
−213
−213
dBc/Hz typ
−89 −89 dBc/Hz typ
−87 −87 dBc/Hz typ
−90 −90 dBc/Hz typ
−78 −78 dBc/Hz typ
−85 −85 dBc/Hz typ
−65 −65 dBc/Hz typ
−84 −84 dBc/Hz typ
−88/−99
−90/−104
−91/−100
−80/−84
−88/−90
−65/−73
−80/−86
−88/−99
−90/−104
−91/−100
−80/−84
−88/−90
−65/−73
−80/−86
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
Test Conditions/Comments
AVDD ≤ VP ≤ 6.0 V
4.5 mA typical
4.5 mA typical
6.5 mA typical
TA = 25°C
@ VCO output
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 300 Hz offset and 30 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 200 Hz offset and 10 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 30 kHz/60 kHz and 30 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 10 kHz/20 kHz and 10 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
1 Operating temperature range for the B version is −40°C to +85°C.
2 Operating temperature range for the Y version is −40°C to +125°C.
3 This is the maximum operating frequency of the CMOS counters.
4 AC coupling ensures AVDD/2 bias. See Figure 35 for typical circuit.
5 Guaranteed by design.
6 TA = 25°C; AVDD = DVDD = 3 V; RFIN for ADF4116 = 540 MHz; RFIN for ADF4117, ADF4118 = 900 MHz.
7 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N
divider value) and 10logFPFD: PNSYNTH = PNTOT – 10logFPFD – 20logN.
8 The phase noise is measured with the EVAL-ADF411xEB and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer
(fREFOUT = 10 MHz @ 0 dBm).
9 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; loop bandwidth = 20 kHz.
10 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop bandwidth = 20 kHz.
11 fREFIN = 10 MHz; fPFD = 30 kHz; offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; loop bandwidth = 3 kHz.
12 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; loop bandwidth = 20 kHz.
13 fREFIN = 10 MHz; fPFD = 10 kHz; offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; loop bandwidth = 1 kHz.
14 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; loop bandwidth = 20 kHz.
Rev. D | Page 4 of 28

4페이지










ADF4116 전자부품, 판매, 대치품
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADF4116/ADF4117/ADF4118
FLO 1
CP 2
CPGND 3
AGND 4
RFINB 5
RFINA 6
AVDD 7
REFIN 8
ADF4116/
ADF4117/
ADF4118
TOP VIEW
(Not to Scale)
16 VP
15 DVDD
14 MUXOUT
13 LE
12 DATA
11 CLK
10 CE
9 DGND
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 FLO
Fast Lock Switch Output. This can be used to switch an external resistor to change the loop filter bandwidth
and speed up locking the PLL.
2 CP
Charge Pump Output. When enabled, this provides the ± ICP to the external loop filter, which in turn drives the
external VCO.
3
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
4
AGND
Analog Ground. This is the ground return path for the prescaler.
5 RFINB Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF. See Figure 26.
6 RFINA Input to the RF Prescaler. This small signal input is ac-coupled from the VCO.
7 AVDD
Analog Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AVDD must have the same value as DVDD.
8 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 kΩ.
See Figure 25. The oscillator input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
9
DGND
Digital Ground.
10 CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state
mode. Taking the pin high powers up the device depending on the status of the power-down bit F2.
11 CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
21-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This input is a high
impedance CMOS input.
13 LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches, the latch being selected using the control bits.
14 MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
15 DVDD
Digital Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground plane (1 μF, 1 nF)
should be placed as close as possible to this pin. For best performance, the 1 μF capacitor should be placed within 2 mm
of the pin. The placing of the 1 nF capacitor is less critical, but should still be within 5 mm of the pin.
DVDD must have the same value as AVDD.
16 VP
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, this supply can
be set to 6 V and used to drive a VCO with a tuning range of up to 6 V.
Rev. D | Page 7 of 28

7페이지


구       성 총 28 페이지수
다운로드[ ADF4116.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
ADF4110

RF PLL Frequency Synthesizers

Analog Devices
Analog Devices
ADF4111

RF PLL Frequency Synthesizers

Analog Devices
Analog Devices

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵