|기능||uP-Compatible Multiplying Quad 12-Bit D/A Converter|
전체 12 페이지
Quad 12-Bit D/A Converter
Four, complete, 12-bit CMOS DACs with buffer registers
Linearity error: ±1/2 LSB TMIN, TMAX (AD394T)
Factory-trimmed gain and offset
Precision output amplifiers for VOUT
Full four-quadrant multiplication per DAC
Monoticity guaranteed over full temperature range
Fast settling: 15 µs maximum to ±1/2 LSB
Available in MIL-STD-883B
The AD394 contains four 12-bit, high-speed, low power, voltage
Ooutput, multiplying digital-to-analog converters in a compact
B28-pin hybrid package. The design is based on a proprietary,
latched, 12-bit, CMOS DAC chip, which reduces chip count and
Sprovides high reliability. The AD394 is ideal for systems
Orequiring digital control of many analog voltages where board
space is at a premium and low power consumption is a neces-
Lsity. Such applications include automatic test equipment, process
Econtrollers, and vector stroke displays.
TEThe AD394 is laser-trimmed to ±1/2 LSB maximum differential
and integral linearity (AD394T) and full-scale accuracy of
±0.05 percent at 25°C. The high initial accuracy is possible
because of the use of precision, laser-trimmed, thin-film scaling
Figure 1. Functional Block Diagram
The individual DAC registers are accessed by the CS1 through
CS4 control pins. These control signals allow any combination
of the DAC select matrix to occur (see Table 3). Once selected,
the DAC is loaded with a single 12-bit wide word. The 12-bit
parallel digital input interfaces to most 12- and 16-bit bus
1. The AD394 offers a dramatic reduction in printed circuit
board space in systems using multiple low power DACs.
2. Each DAC is independently addressable and provides
versatile control architecture for a simple interface to
microprocessors. All latch enable signals are level-
The AD394 outputs (VREFIN = 10 V) provide a ±10 V bipolar
output range with positive-true offset binary input coding.
3. The output voltage is trimmed to a full-scale accuracy of
±0.05%. Settling time to ±1/2 LSB is 15 µs maximum.
The AD394 is packaged in a 28-lead ceramic package and is
available for operation over a −55°C to +125°C temperature
4. A maximum gain TC of 5 ppm/°C is achievable.
5. Two- or four-quadrant multiplication can be achieved
simply by applying the appropriate input voltage signal to
the selected DAC's reference (VREFIN).
6. The AD394TD features guaranteed accuracy and linearity
over the −55°C to +125°C temperature range.
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
POWER SUPPLY GAIN SENSITIVITY
Operating (Full Specifications)
AD394TD and AD394TD/883B1
−55 125 °C
−65 150 °C
1 The AD394 T grade is available to MIL-STD-883, Method 5008, Class B. See Analog Devices Military Catalog (1985) for proper part number and detail specification.
2 Timing specifications appear in Table 5 and Figure 6.
3 See the Theory of Operation section for code tables and graphs.
4 FSR means full-scale range and is equal to 20 V for a ±10 V bipolar range and 10 V for a 0 V to 10 V unipolar range.
5 Integral nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function.
6 This is a measure of the amount of charge injected from the digital inputs to the analog outputs when the inputs change state. It is usually specified as the area of the
glitch in nVs and is measured with VREFIN = AGND.
7 Digital crosstalk is defined as the change in any one output’s steady state value as a result of any other output being driven from VOUTMIN to VOUTMAX into a 2kΩ load by
means of varying the digital input code.
O8 Reference crosstalk is defined as the change in any one output as a result of any other output being driven from VOUTMIN to VOUTMAX @10 kHz into a 2 kΩ load by means
of varying the amplitude of the reference signal.
BSOLETE9 The AD394 can be used with supply voltages as low as ±11.4 V. See Figure 10.
Rev. A | Page 4 of 12
THEORY OF OPERATION
The AD394 quad DAC provides four-quadrant multiplication.
It is a hybrid IC comprised of four, monolithic, 12-bit, CMOS,
multiplying DACs and eight precision output amplifiers. Each
of the four independent-buffered channels has an independent
reference input capable of accepting a separate dc or ac signal
for multiplying or for function generation applications. The
CMOS DACs act as digitally programmable attenuators when
used with a varying input signal or, if used with a fixed dc
reference, the DAC would act as a standard bipolar output DAC.
In addition, each DAC has a 12-bit wide data latch to buffer the
converter when connected to a microprocessor data bus.
Figure 5 shows the transfer function. The diagram indicates an
area over which many different combinations of the reference
Oinput and digital input can result in a particular analog output
voltage. The highlighted transfer line in the diagram indicates
Bthe transfer function if a fixed reference is at the input. The
Sdigital code above the diagram indicates the midpoint and
endpoints of each function. The relationship between the
Oreference input (VREFIN), the digital input code, and the analog
Loutput is given in Table 4. Note that the reference input signal
sets the slope of the transfer function (and determines the full-
Escale output at code 111...111), while the digital input selects the
TEhorizontal position in each diagram.
Figure 5. The AD394 as a Four-Quadrant Multiplier
of Reference and Digital Input
DATA AND CONTROL SIGNAL FORMAT
The AD394 accepts 12-bit parallel data in response to Control
Signals CS1–CS4. As detailed in Table 3, the four chip select
lines are used to address the DAC register of interest. It is per-
missible to have more than one chip select active at any time. If
CS1–CS4 are all brought low coincident, all four DAC outputs
will be updated to the value located on the data bus. All control
inputs are level-triggered and may be hard-wired low to render
any register (or group of registers) transparent.
Table 3. DAC Select Matrix
CS1 CS2 CS3 CS4 Operation
1 1 1 1 All DACs latched
0 1 1 1 Load DAC 1 from data bus
1 0 1 1 Load DAC 2 from data bus
1 1 0 1 Load DAC 3 from data bus
1 1 1 0 Load DAC 4 from data bus
0 0 0 0 All DACs simultaneously loaded
Table 4. Bipolar Code Table
Analog Output Voltage, VREFIN = 10 V
1111 1111 1 × (VREFIN)
Full Scale − 1 LSB
0000 0000 1 × (VREFIN)
0000 0001 1 × (VREFIN)
0000 0000 1 × (VREFIN)
1111 1111 −1 × (VREFIN)
0000 0000 −1 × (VREFIN)
0000 0000 −1 × (VREFIN)
Rev. A | Page 7 of 12
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|부품번호||상세설명 및 기능||제조사|
Quad 12-Bit Microprocessor-Compatible D/A Converter
Complete Quad 12-Bit D/A Converter
|DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵|