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AD1377 PDF 데이터시트 ( Data , Function )

부품번호 AD1377 기능
기능 High Speed 16-Bit A/D Converters
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AD1377 데이터시트, 핀배열, 회로
Complete, High Speed
16-Bit A/D Converters
AD1376/AD1377
FEATURES
Complete 16-bit converters with reference and clock
±0.003% maximum nonlinearity
Digital output data is provided in parallel form with
corresponding clock and status outputs. All digital inputs and
outputs are TTL-compatible.
No missing codes to 14 bits over temperature
Fast conversion
17 µs to 16 bits (AD1376)
10 µs to 16 bits (AD1377)
Short cycle capability
Adjustable clock rate
Parallel outputs
For the AD1376, the serial output function is no longer
available after date code 0111. For the AD1377, the serial output
function is no longer available after date code 0210. The option
of applying an external clock on the CONVERT START pin to
slow down the internally set conversion time is no longer
supported for either part.
Low power
645 mW typical (AD1376)
585 mW typical (AD1377)
Industry-standard pinout
PRODUCT HIGHLIGHTS
1. The AD1376/AD1377 provide 16-bit resolution with a
maximum linearity error of ±0.003% (1/2 LSB14) at 25°C.
GENERAL DESCRIPTION
The AD1376/AD1377 are high resolution, 16-bit analog-to-
digital converters with internal reference, clock, and laser-
trimmed thin-film applications resistors. The AD1376/AD1377
are excellent for use in high resolution applications requiring
moderate speed and high accuracy or stability over commercial
temperature ranges (0°C to 70°C). They are packaged in
compact 32-lead, ceramic seam-sealed (hermetic), dual in-line
packages (DIP). Thin-film scaling resistors provide bipolar
input ranges of ±2.5 V, ±5 V, and ±10 V and unipolar input
ranges of 0 V to +5 V, 0 V to +10 V, and 0 V to +20 V.
2. The AD1376 conversion time is 14 µs (typical) short cycled
to 14 bits, and 16 µs to 16 bits.
3. The AD1377 conversion time is 8 µs (typical) short cycled
to 14 bits, and 9 µs to 16 bits.
4. Two binary codes are available on the digital output. They
are CSB (complementary straight binary) for unipolar input
voltage ranges and COB (complementary offset binary) for
bipolar input ranges. Complementary twos complement
(CTC) coding may be obtained by inverting Pin 1 (MSB).
5. The AD1376/AD1377 include internal reference and clock
with external clock rate adjust pin, and parallel digital outputs.
FUNCTIONAL BLOCK DIAGRAM
(MSB) BIT 1 1
BIT 2 2
BIT 3 3
BIT 4 4
BIT 5 5
BIT 6 6
BIT 7 7
BIT 8 8
BIT 9 9
BIT 10 10
BIT 11 11
BIT 12 12
(LSB FOR 13 BITS) BIT 13 13
(LSB FOR 14 BITS) BIT 14 14
BIT 15 15
BIT 16 16
AD1376/AD1377
16-BIT SAR
COMPARATOR
32 SHORT CYCLE
31 CONVERT START
REFERENCE
30 +5V DC SUPPLY VL
29 GAIN ADJUST
7.5k
28 +15V DC SUPPLY VCC
27 COMPARATOR IN
26 BIPOLAR OFFSET
25 +10V
3.75k3.75k
24 +20V
23 CLK RATE CTRL
22 ANALOG COMMON
21 –15V DC SUPPLY VEE
20 CLOCK OUT
CLOCK
19 DIGITAL COMMON
18 STATUS
17 NC
Figure 1.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.481.3113 © 2005 Analog Devices, Inc. All rights reserved.




AD1377 pdf, 반도체, 판매, 대치품
AD1376/AD1377
AD1376JD/AD1377JD
AD1376KD/AD1377KD
Model
Min Typ
Max Min Typ
Max
DRIFT6
Gain
±15 ±5
±15
Offset
Unipolar
±2 ±4 ±2 ±4
Bipolar
±10 ±3
±10
Linearity
±2
±3 ±0.3
±2
Guaranteed No Missing Code
Temperature Range
0 to 70 (13 Bits)
0 to 70 (14 Bits)
DIGITAL OUTPUT1
(All Codes Complementary)
Parallel Output Codes7
Unipolar
Bipolar
CSB
COB, CTC8
CSB
COB, CTC8
Output Drive
5
5
Status
Status Output Drive
Internal Clock9
Logic 1 During
Conversion
5
Logic 1 During
Conversion
5
Clock Output Drive
55
Frequency
1040/1750
1040/1750
TEMPERATURE RANGE
Specification
0 to 70
0 to 70
Operating
−25 to +85
−25 to +85
Storage
−55 to +125
−55 to +125
1 Logic 0 = 0.8 V max; Logic 1 = 2.0 V min for inputs. For digital outputs, Logic 0 = 0.4 V max. Logic 1 = 2.4 V min.
2 Tested on ±10 V and 0 V to +10 V ranges.
3 Adjustable to zero.
4 Full-scale range.
5 Conversion time may be shortened with “short cycle” set for lower resolution.
6 Guaranteed but not 100% production tested.
7 CSB–Complementary Straight Binary. COB–Complementary Offset Binary. CTC–Complementary Twos Complement.
8 CTC coding obtained by inverting MSB (Pin 1).
9 With Pin 23, clock rate controls tied to digital ground.
Unit
ppm/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
°C
LSTTL Loads
LSTTL Loads
LSTTL Loads
kHz
°C
°C
°C
Rev. D | Page 4 of 12

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AD1377 전자부품, 판매, 대치품
In either adjustment circuit, the fixed resistor connected to
Pin 27 should be located close to this pin to keep the pin
connection short. Pin 27 is quite sensitive to external noise
pickup and should be guarded by ANALOG COMMON.
TIMING
The timing diagram is shown in Figure 8. Receipt of a
CONVERT START signal sets the STATUS flag, indicating
conversion in progress. This in turn removes the inhibit applied
to the gated clock, permitting it to run through 17 cycles. All
the SAR parallel bits, the STATUS flip-flops, and the gated clock
inhibit signal are initialized on the trailing edge of the
CONVERT START signal. At time t0, B1 is reset and B2–B16 are
set unconditionally. At t1, the Bit 1 decision is made (keep) and
Bit 2 is reset unconditionally. This sequence continues until the
Bit 16 (LSB) decision (keep) is made at t16. The STATUS flag is
reset, indicating that the conversion is complete and that the
parallel output data is valid. Resetting the STATUS flag restores
the gated clock inhibit signal, forcing the clock output to the
low Logic 0 state. Note that the clock remains low until the next
conversion.
Corresponding parallel data bits become valid on the same
positive-going clock edge.
(1)
CONVERT
START
MAXIMUM THROUGHPUT TIME
CONVERSION TIME (2)
INTERNAL
CLOCK
STATUS
MSB
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14
BIT 15
LSB
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16
(2)
0
(3) t17
1
1
0
0
1
1
1
0
1
1
1
1
0
MSB
1
0
01 1 0 01 1 10 1 1 1 1 0 1 0
LSB
NOTES:
1. THE CONVERT START PULSEWIDTH IS 50ns MIN AND MUST REMAIN LOW DURING A
CONVERSION. THE CONVERSION IS INITIATED BY THE TRAILING EDGE OF THE
CONVERT COMMAND.
2. MSB DECISION.
3. CLOCK REMAINS LOW AFTER LAST BIT DECISION.
Figure 8. Timing Diagram (Binary Code 0110011101111010)
AD1376/AD1377
DIGITAL OUTPUT DATA
Parallel data from TTL storage registers is in negative true form
(Logic 1 = 0 V and Logic 0 = 2.4 V). Parallel data output coding
is complementary binary for unipolar ranges and complement-
tary offset binary for bipolar ranges. Parallel data becomes valid
at least 20 ns before the STATUS flag returns to Logic 0,
permitting parallel data transfer to be clocked on the 1 to 0
transition of the STATUS flag (see Figure 9). Parallel data
output changes state on positive going clock edges.
BIT 16
VALID
BUSY
(STATUS)
20ns MIN TO 90ns
Figure 9. LSB Valid to Status Low
Short Cycle Input
Pin 32 (SHORT CYCLE) permits the timing cycle shown in
Figure 8 to be terminated after any number of desired bits has
been converted, allowing somewhat shorter conversion times in
applications not requiring full 16-bit resolution. When 10-bit
resolution is desired, Pin 32 is connected to Bit 11 output
Pin 11. The conversion cycle then terminates and the STATUS
flag resets after the Bit 10 decision (Figure 8). Short cycle
connections and associated 8-, 10-, 12-, 13-, 14-, and 15-bit
conversion times are summarized in Table 3 for a 1.6 MHz
clock (AD1377) or 933 kHz clock (AD1376).
Table 3. Short Cycle Connections
Resolution
(%
Bits FSR)
Maximum
Conversion Time (µs)
AD1377 AD1376
Status
Flag
Reset
16 0.0015 10
17.1 t16
15 0.003 9.4
16.1 t15
14 0.006 8.7
15.0 t1
13 0.012 8.1
13.9 t13
12 0.024 7.5
12.9 t12
10 0.100 6.3
10.7 t10
8 0.390 5.0 8.6 t8
Connect
Short Cycle
Pin 32 to
NC (Open)
Pin 16
Pin 15
Pin 14
Pin 13
Pin 11
Pin 9
INPUT SCALING
The ADC inputs should be scaled as close to the maximum
input signal range as possible to use the maximum signal
resolution of the ADC. Connect the input signal as shown in
Table 4. See Figure 10 for circuit details.
Rev. D | Page 7 of 12

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High Speed 16-Bit A/D Converters

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