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AD9218 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9218은 전자 산업 및 응용 분야에서
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부품번호 AD9218 기능
기능 3V Dual Analog-to-Digital Converter
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AD9218 데이터시트, 핀배열, 회로
10-Bit, 40/65/80/105 MSPS
3 V Dual Analog-to-Digital Converter
AD9218
FEATURES
Dual 10-bit, 40 MSPS, 65 MSPS, 80 MSPS, and 105 MSPS ADC
Low power: 275 mW at 105 MSPS per channel
On-chip reference and track-and-hold
300 MHz analog bandwidth each channel
SNR = 57 dB @ 41 MHz, Encode = 80 MSPS
1 V p-p or 2 V p-p analog input range each channel
3.0 V single-supply operation (2.7 V to 3.6 V)
Power-down mode for single-channel operation
Twos complement or offset binary output mode
Output data alignment mode
Pin compatible with the 8-bit AD9288
–75 dBc crosstalk between channels
APPLICATIONS
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
I and Q communications
Ultrasound equipment
GENERAL DESCRIPTION
The AD9218 is a dual 10-bit monolithic sampling analog-to-
digital converter with on-chip track-and-hold circuits. The
product is low cost, low power, and is small and easy to use. The
AD9218 operates at a 105 MSPS conversion rate with
outstanding dynamic performance over its full operating range.
Each channel can be operated independently.
The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power
supply and a clock for full operation. No external reference or
driver components are required for many applications. The
digital outputs are TTL/CMOS compatible and a separate
output power supply pin supports interfacing with 3.3 V or
2.5 V logic.
The clock input is TTL/CMOS compatible and the 10-bit digital
outputs can be operated from 3.0 V (2.5 V to 3.6 V) supplies.
User-selectable options offer a combination of power-down
modes, digital data formats, and digital data timing schemes.
In power-down mode, the digital outputs are driven to a high
impedance state.
FUNCTIONAL BLOCK DIAGRAM
ENCODE A
AINA
AINA
REFINA
REFOUT
REFINB
AINB
AINB
ENCODE B
TIMING
T/H
T/H
TIMING
AD9218
ADC
/
10
OUTPUT
REGISTER
/
10
REF
ADC
/
10
OUTPUT
REGISTER
/
10
D9A TO D0A
USER
SELECT NO. 1
USER
SELECT NO. 2
DATA
FORMAT/
GAIN
D9B TO D0B
VD GND VDD
Figure 1.
PRODUCT HIGHLIGHTS
1. Low Power. Only 275 mW power dissipation per channel
at 105 MSPS. Other speed grades proportionally scaled
down while maintaining high ac performance.
2. Pin Compatibility Upgrade. Allows easy migration from 8-bit
to 10-bit devices. Pin compatible with the 8-bit AD9288
dual ADC.
3. Easy to Use. On-chip reference and user controls provide
flexibility in system design.
4. High Performance. Maintains 54 dB SNR at 105 MSPS
with a Nyquist input.
5. Channel Crosstalk. Very low at –75 dBc.
6. Fabricated on an Advanced CMOS Process. Available in a
48-lead low profile quad flat package (7 mm × 7 mm
LQFP) specified over the industrial temperature range
(−40°C to +85°C).
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.




AD9218 pdf, 반도체, 판매, 대치품
AD9218
SPECIFICATIONS
DC SPECIFICATIONS
VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes1
Offset Error2
Gain Error2
Differential Nonlinearity
(DNL)
Integral Nonlinearity
(INL)
TEMPERATURE DRIFT
Offset Error
Gain Error2
Reference
REFERENCE
Internal Reference Voltage
(REFOUT)
Input Resistance (REFINA,
REFINB)
ANALOG INPUTS
Differential Input Voltage
Range (AIN, AIN)3
Common-Mode Voltage3
Input Resistance
Input Capacitance
POWER SUPPLY
VD
VDD
Supply Currents
IVD (VD = 3.0 V)4
IVDD (VDD = 3.0 V)4
Power Dissipation DC5
IVD Power-Down Current6
Power Supply Rejection
Ratio
Temp
Full
25°C
25°C
25°C
Full
25°C
Full
Full
Full
Full
25°C
Full
Full
Full
Full
25°C
Full
Full
Full
25°C
Full
Full
25°C
Test
Level Min
AD9218BST-40/-65
Typ Max
10
VI Guaranteed, not tested
I –18 2
18
I –2
3
8
I –1
±0.3/±0.6 1/1.3
VI ±0.8
I –1/–1.6 ±0.3/±1 1/1.6
VI ±1
V 10
V 80
V 40
I 1.18 1.24
1.28
VI 9
11
13
V
V
VI 8
V
IV 2.7
IV 2.7
VI
V
VI
VI
I
1 or 2
VD/3
10
3
3
3
108/117
7/11
325/350
20
±1
14
3.6
3.6
113/130
340/390
AD9218BST-80/-105
Min Typ
Max
10
Unit
Bits
Guaranteed, not tested
–18 2
18
–2 3.5 8
–1 ±0.5/±0.8 1.2/1.7
LSB
% FS
LSB
±0.6/±0.9
–1.35/–2.7 ±0.75/±2
LSB
+1.35/2.7 LSB
±1/±2.3
LSB
4 ppm/°C
100 ppm/°C
40 ppm/°C
1.18 1.24
1.28 V
9 11 13 kΩ
1V
VD/3 V
8 10 14 kΩ
3 pF
2.7 3
2.7 3
3.6 V
3.6 V
172/183
13/17
515/550
22
±1
175/188
525/565
mA
mA
mW
mA
mV/V
1 No missing codes across industrial temperature range guaranteed for 40 MSPS, 65 MSPS, and 80 MSPS grades. No missing codes at room temperature guaranteed for
105 MSPS grade.
2 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.25 V external reference) 65 grade in 2 V p-p range, 40, 80, 105 grades in 1 V p-p range.
3 (AIN –AIN) = ±0.5 V in 1 V range (full scale), (AIN – AIN) = ±1 V in 2 V range (full scale). The analog inputs self-bias to VD/3. This common-mode voltage can be overdriven
externally by a low impedance source by ±300 mV (differential drive, gain = 1) or ±150 mV (differential drive, gain = 2).
4 AC power dissipation measured with rated encode and a 10.3 MHz analog input @ 0.5 dBFS, CLOAD = 5 pF.
5 DC power dissipation measured with rated encode and a dc analog input (outputs static, IVDD = 0).
6 In power-down state, IVDD = ±10 μA typical (all grades).
Rev. C | Page 3 of 28

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AD9218 전자부품, 판매, 대치품
AD9218
SWITCHING SPECIFICATIONS
VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.
Table 4.
Parameter
ENCODE INPUT PARAMETERS
Maximum Encode Rate
Minimum Encode Rate
Encode Pulse Width High (tEH)
Encode Pulse Width Low (tEL)
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
DIGITAL OUTPUT PARAMETERS
Output Valid Time (tV)1
Output Propagation Delay (tPD)1
Output Rise Time (tR)
Output Fall Time (tF)
Out-of-Range Recovery Time
Transient Response Time
Recovery Time from Power-Down
Pipeline Delay
Temp
Full
Full
Full
Full
25°C
25°C
Full
Full
25°C
25°C
25°C
25°C
25°C
Full
Test
Level
VI
IV
IV
IV
V
V
VI
VI
V
V
V
V
V
IV
AD9218BST-40/-65
Min Typ Max
40/65
7/6
7/6
2
3
20/20
2.5
4.5 7
1
1.2
5
5
10
5
AD9218BST-80/-105
Min Typ Max
80/105
5/3.8
5/3.8
2
3
20/20
2.5
4.5 6
1.0
1.2
5
5
10
5
Unit
MSPS
MSPS
ns
ns
ns
ps rms
ns
ns
ns
ns
ns
ns
Cycles
Cycles
1 tV and tPD are measured from the 1.5 level of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed
an ac load of 5 pF or a dc current of ±40 μA. Rise and fall times are measured from 10% to 90%.
TIMING DIAGRAMS
SAMPLE N
SAMPLE
N+1
SAMPLE
N+5
SAMPLE
N+6
AINA
AINB
tA
tEH
ENCODE A
ENCODE B
SAMPLE
SAMPLE
tEL 1/fS N + 2 N + 3
SAMPLE
N+4
D9A TO D0A
DATA N – 5
DATA N – 4
DATA N – 3
DATA N – 2
tPD
DATA N – 1
DATA N
tV
D9B TO D0B
DATA N – 5
DATA N – 4
DATA N – 3
DATA N – 2
DATA N – 1
Figure 2. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing
DATA N
Rev. C | Page 6 of 28

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