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PDF AD9248 Data sheet ( Hoja de datos )
| Número de pieza | AD9248 | |
| Descripción | Dual A/D Converter | |
| Fabricantes | Analog Devices | |
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14-Bit, 20 MSPS/40 MSPS/65 MSPS
Dual A/D Converter
AD9248
FEATURES
Integrated dual 14-bit ADC
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 71.6 dB (to Nyquist, AD9248-65)
SFDR = 80.5 dBc (to Nyquist, AD9248-65)
Low power: 300 mW/channel at 65 MSPS
Differential input with 500 MHz, 3 dB bandwidth
Exceptional crosstalk immunity > 85 dB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
Output datamux option
APPLICATIONS
Ultrasound equipment
Direct conversion or IF sampling receivers
WB-CDMA, CDMA2000, WiMAX
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
GENERAL DESCRIPTION
The AD9248 is a dual, 3 V, 14-bit, 20 MSPS/40 MSPS/65 MSPS
analog-to-digital converter (ADC). It features dual high
performance sample-and hold amplifiers (SHAs) and an
integrated voltage reference. The AD9248 uses a multistage
differential pipelined architecture with output error correction
logic to provide 14-bit accuracy and to guarantee no missing
codes over the full operating temperature range at up to
65 MSPS data rates. The wide bandwidth, differential SHA
allows for a variety of user-selectable input ranges and offsets,
including single-ended applications. It is suitable for various
applications, including multiplexed systems that switch full-
scale voltage levels in successive channels and for sampling
inputs at frequencies well beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available and can
compensate for wide variations in the clock duty cycle, allowing
the converter to maintain excellent performance. The digital
output data is presented in either straight binary or twos
complement format. Out-of-range signals indicate an overflow
condition, which can be used with the most significant bit to
determine low or high overflow.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND
VIN+_A
VIN–_A
SHA
ADC
14 14
OUTPUT
MUX/
BUFFERS
OTR_A
D13_A TO D0_A
OEB_A
REFT_A
REFB_A
VREF
SENSE
AGND
0.5V
REFT_B
REFB_B
VIN+_B
VIN–_B
SHA
AD9248
CLOCK
DUTY CYCLE
STABILIZER
MODE
CONTROL
MUX_SELECT
CLK_A
CLK_B
DCS
SHARED_REF
PWDN_A
PWDN_B
DFS
ADC
14 OUTPUT 14
MUX/
BUFFERS
OTR_B
D13_B TO D0_B
OEB_B
DRVDD DRGND
Figure 1.
Fabricated on an advanced CMOS process, the AD9248 is
available in a Pb-free, space saving, 64-lead LQFP or LFCSP and
is specified over the industrial temperature range (−40°C to
+85°C).
PRODUCT HIGHLIGHTS
1. Pin-compatible with the AD9238, 12-bit 20 MSPS/
40 MSPS/65 MSPS ADC.
2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS
allow flexibility between power, cost, and performance to suit
an application.
3. Low power consumption: AD9248-65: 65 MSPS = 600 mW,
AD9248-40: 40 MSPS = 330 mW, and AD9248-20: 20 MSPS =
180 mW.
4. Typical channel isolation of 85 dB @ fIN = 10 MHz.
5. The clock duty cycle stabilizer (AD9248-20/AD9248-40/
AD9248-65) maintains performance over a wide range of
clock duty cycles.
6. Multiplexed data output option enables single-port operation
from either Data Port A or Data Port B.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved.
1 page  
AD9248
Parameter
MATCHING CHARACTERISTICS
Offset Error
(Nonshared Reference Mode)
Offset Error
(Shared Reference Mode)
Gain Error
(Nonshared Reference Mode)
Gain Error
(Shared Reference Mode)
Test AD9248BST/BCP-20 AD9248BST/BCP-40 AD9248BST/BCP-65
Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
25°C I
25°C I
25°C I
25°C I
±0.19 ±1.56
±0.19 ±1.56
±0.07 ±1.43
±0.01 ±0.06
±0.19 ±1.56
±0.19 ±1.56
±0.07 ±1.43
±0.01 ±0.06
±0.25 ±1.74 % FSR
±0.25 ±1.74 % FSR
±0.07 ±1.47 % FSR
±0.01 ±0.10 % FSR
1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
2 Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure 29 for the equivalent analog input structure.
4 Measured with dc input at maximum clock rate.
5 Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).
Rev. B | Page 4 of 48
5 Page 
AD9248
Table 6. 64-Lead LQFP and 64-Lead LFCSP Pin Function Descriptions
Pin No.
Mnemonic Description
1, 4, 13, 16 AGND
Analog Ground.
2
VIN+_A
Analog Input Pin (+) for Channel A.
3
VIN−_A
Analog Input Pin (−) for Channel A.
5, 12, 17, 64 AVDD
Analog Power Supply.
6
REFT_A
Differential Reference (+) for Channel A.
7
REFB_A
Differential Reference (−) for Channel A.
8
VREF
Voltage Reference Input/Output.
9
SENSE
Reference Mode Selection.
10
REFB_B
Differential Reference (−) for Channel B.
11
REFT_B
Differential Reference (+) for Channel B.
14
VIN−_B
Analog Input Pin (−) for Channel B.
15
VIN+_B
Analog Input Pin (+) for Channel B.
18
CLK_B
Clock Input Pin for Channel B.
19 DCS Enable Duty Cycle Stabilizer (DCS) Mode.
20 DFS
Data Output Format Select Pin (Low for Offset Binary, High for Twos Complement).
21
PDWN_B
Power-Down Function Selection for Channel B.
Logic 0 enables Channel B. Logic 1 powers down Channel B (outputs static, not High-Z).
22
OEB_B
Output Enable Pin for Channel B.
Logic 0 enables Data Bus B. Logic 1 sets outputs to High-Z.
23 to 27,
30 to 38
D0_B (LSB) to Channel B Data Output Bits.
D13_B (MSB)
28, 40, 53 DRGND
Digital Output Ground.
29, 41, 52 DRVDD
Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 μF capacitor.
Recommended decoupling is 0.1 μF capacitor in parallel with 10 μF capacitor.
39
OTR_B
Out-of-Range Indicator for Channel B.
42 to 51,
54 to 57
D0_A (LSB) to Channel A Data Output Bits.
D13_A (MSB)
58
OTR_A
Out-of-Range Indicator for Channel A.
59
OEB_A
Output Enable Pin for Channel A.
Logic 0 enables Data Bus A. Logic 1 sets outputs to High-Z.
60
PDWN_A
Power-Down Function Selection for Channel A.
Logic 0 enables Channel A. Logic 1 powers down Channel A (outputs static, not High-Z).
61 MUX_SELECT Data Multiplexed Mode.
(See Data Format section for how to enable; high setting disables output data multiplexed mode.)
62 SHARED_REF Shared Reference Control Pin (Low for Independent Reference Mode, High for Shared Reference Mode).
63
CLK_A
Clock Input Pin for Channel A.
EP For the 64-Lead LFCSP only, there is an exposed pad that must connect to AGND.
Rev. B | Page 10 of 48
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9248.PDF ] | |
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