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PDF AD9430 Data sheet ( Hoja de datos )
| Número de pieza | AD9430 | |
| Descripción | 3.3V A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9430 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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FEATURES
SNR = 65 dB @ fIN = 70 MHz @ 210 MSPS
ENOB of 10.6 @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS)
SFDR = 80 dBc @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS)
Excellent linearity:
DNL = ±0.3 LSB (typical)
INL = ±0.5 LSB (typical)
2 output data options:
Demultiplexed 3.3 V CMOS outputs each @ 105 MSPS
Interleaved or parallel data output option
LVDS at 210 MSPS
700 MHz full-power analog bandwidth
On-chip reference and track-and-hold
Power dissipation = 1.3 W typical @ 210 MSPS
1.5 V input voltage range
3.3 V supply operation
Output data format option
Data sync input and data clock output provided
Clock duty cycle stabilizer
GENERAL DESCRIPTION
The AD9430 is a 12-bit, monolithic, sampling analog-to-digital
converter (ADC) optimized for high performance, low power,
and ease of use. The product operates up to a 210 MSPS
conversion rate and is optimized for outstanding dynamic
performance in wideband carrier and broadband systems. All
necessary functions, including a track-and-hold (T/H) and
reference, are included on the chip to provide a complete
conversion solution.
The ADC requires a 3.3 V power supply and a differential
ENCODE clock for full performance operation. The digital
outputs are TTL/CMOS or LVDS compatible and support either
twos complement or offset binary format. Separate output
power supply pins support interfacing with 3.3 V CMOS logic.
Two output buses support demultiplexed data up to 105 MSPS
rates in CMOS mode. A data sync input is supported for proper
output data port alignment in CMOS mode, and a data clock
output is available for proper output data timing. In LVDS
mode, the chip provides data at the ENCODE clock rate.
Fabricated on an advanced BiCMOS process, the AD9430 is
available in a 100-lead, surface-mount plastic package
(100 e-PAD TQFP) specified over the industrial temperature
range (–40°C to +85°C).
12-Bit, 170/210 MSPS
3.3 V A/D Converter
AD9430
FUNCTIONAL BLOCK DIAGRAM
SENSE VREF AGND DRGND DRVDD AVDD
AD9430
SCALABLE
REFERENCE
VIN+
VIN–
DS+
DS–
CLK+
CLK–
TRACK-
AND-HOLD
ADC
12-BIT
PIPELINE
CORE
12
LVDS
OUTPUTS
CMOS
OUTPUTS
CLOCK
MANAGEMENT
SELECT CMOS
OR LVDS
DATA,
OVERRANGE
IN LVDS OR
2-PORT CMOS
DCO+
DCO–
S1 S2
S4 S5
Figure 1.
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
PRODUCT HIGHLIGHTS
1. High performance.
Maintains 65 dB SNR @ 210 MSPS with a 65 MHz input.
2. Low power.
Consumes only 1.3 W @ 210 MSPS.
3. Ease of use.
LVDS output data and output clock signal allow interface
to current FPGA technology. The on-chip reference and
sample-and-hold provide flexibility in system design. Use
of a single 3.3 V supply simplifies system power supply
design.
4. Out of range (OR) feature.
The OR output bit indicates when the input signal is
beyond the selected input range.
5. Pin compatible with 10-bit AD9411 (LVDS only).
.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved.
1 page  
AD9430
DC SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, LVDS output mode,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
Reference Out (VREF)
REFERENCE
Reference Out (VREF)
Output Current1
IVREF Input Current2
ISENSE Input Current2
ANALOG INPUTS (VIN+, VIN–)3
Differential Input Voltage Range
(S5 = GND)
Differential Input Voltage Range
(S5 = AVDD)
Input Common-Mode Voltage
Input Resistance
Input Capacitance
POWER SUPPLY (LVDS Mode)
AVDD
DRVDD
Supply Currents
IANALOG (AVDD = 3.3 V)4
IDIGITAL (DRVDD = 3.3 V)4
Power Dissipation4
Power Supply Rejection
AD9430-170
AD9430-210
Test
Temp Level Min
Typ
Max Min Typ
Max Unit
12 Bits
Full VI
25°C I
25°C I
25°C I
Full VI
25°C I
Full VI
–3
–5
–1
–1
–1.5
–2.25
Guaranteed
± 0.3
± 0.3
± 0.5
± 0.5
+3
+5
+1
+1.5
+1.5
+2.25
–3
–5
–1
–1
–1.75
–2.5
Guaranteed
± 0.3
± 0.3
± 0.3
± 0.3
+3
+5
+1
+1.5
+1.75
+2.5
mV
% FS
LSB
LSB
LSB
LSB
Full V
Full V
Full V
58
0.02
+0.12/–0.24
58
0.02
+0.12/–0.24
μV/°C
%/°C
mV/°C
25°C I
25°C IV
25°C I
25°C I
1.15 1.235
1.6
1.3 1.15 1.235
3.0
20
5.0 1.6
1.3 V
3.0 mA
20 μA
5.0 mA
Full V
Full V
Full VI
Full VI
25°C V
1.536
0.766
2.65 2.8
2.2 3
5
1.536
0.766
2.9 2.65 2.8
3.8 2.2 3
5
V
V
2.9 V
3.8 kΩ
pF
Full IV 3.1 3.3
Full IV 3.0 3.3
3.6 3.2 3.3
3.6 3.0 3.3
3.6 V
3.6 V
Full VI
Full VI
Full VI
25°C V
335 372
55 62
1.29 1.43
–7.5
390 450 mA
55 62 mA
1.5 1.7 W
–7.5 mV/V
Rev. E | Page 4 of 44
5 Page 
AD9430
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
AVDD, DRVDD
Analog Inputs
Digital Inputs
REFIN Inputs
Digital Output Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Maximum Case Temperature
θJA 1
Rating
4V
−0.5 V to AVDD + 0.5 V
−0.5 V to DRVDD + 0.5 V
–0.5 V to AVDD + 0.5 V
20 mA
−40°C to +85°C
−65°C to +150°C
150°C
150°C
25°C/W, 32°C/W
1 Typical θJA = 32°C/W (heat slug not soldered); typical θJA = 25°C/W (heat slug
soldered) for multilayer board in still air with solid ground plane.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational section
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
Table 6.
Level Description
I 100% production tested.
II 100% production tested at 25°C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and
characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by
design and characterization testing for industrial
temperature range; 100% production tested at
temperature extremes for military devices.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. E | Page 10 of 44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9430.PDF ] | |
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