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기능 RF Digital-to-Analog Converters
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AD9737A 데이터시트, 핀배열, 회로
Data Sheet
11-/14-Bit, 2.5 GSPS,
RF Digital-to-Analog Converters
AD9737A/AD9739A
FEATURES
Direct RF synthesis at 2.5 GSPS update rate
DC to 1.25 GHz in baseband mode
1.25 GHz to 3.0 GHz in mix-mode
Industry leading single/multicarrier IF or RF synthesis
Dual-port LVDS data interface
Up to 1.25 GSPS operation
Source synchronous DDR clocking
Pin compatible with the AD9739
Programmable output current: 8.7 mA to 31.7 mA
Low power: 1.1 W at 2.5 GSPS
APPLICATIONS
Broadband communications systems
DOCSIS CMTS systems
Military jammers
Instrumentation, automatic test equipment
Radar, avionics
SDIO
SDO
CS
SCLK
FUNCTIONAL BLOCK DIAGRAM
RESET
IRQ
AD9737A/AD9739A
1.2V
SPI
DAC BIAS
VREF
I120
IOUTN
DCI
TxDAC
CORE
IOUTP
DCO
CLK DISTRIBUTION
(DIV-BY-4)
DLL
(MU CONTROLLER)
GENERAL DESCRIPTION
The AD9737A/AD9739A are 11-bit and 14-bit, 2.5 GSPS high
performance RF DACs that are capable of synthesizing wideband
signals from dc up to 3 GHz. The AD9737A/AD9739A are pin
and functionally compatible with the AD9739 with the
exception that the AD9737A/AD9739A do not support
synchronization or RZ mode, and are specified to operate
between 1.6 GSPS and 2.5 GSPS.
By elimination of the synchronization circuitry, some nonideal
artifacts such as images and discrete clock spurs remain stationary
on the AD9737A/AD9739A between power-up cycles, thus
allowing for possible system calibration. AC linearity and noise
performance remain the same between the AD9739 and the
AD9737A/AD9739A.
The inclusion of on-chip controllers simplifies system integration.
A dual-port, source synchronous, LVDS interface simplifies the
digital interface with existing FGPA/ASIC technology. On-chip
controllers are used to manage external and internal clock domain
variations over temperature to ensure reliable data transfer from
the host to the DAC core. A serial peripheral interface (SPI) is
used for device configuration as well as readback of status
registers.
Figure 1.
DACCLK
The AD9737A/AD9739A are manufactured on a 0.18 µm
CMOS process and operate from 1.8 V and 3.3 V supplies.
They are supplied in a 160-ball chip scale ball grid array for
reduced package parasitics.
PRODUCT HIGHLIGHTS
1. Ability to synthesize high quality wideband signals with
bandwidths of up to 1.25 GHz in the first or second
Nyquist zone.
2. A proprietary quad-switch DAC architecture provides
exceptional ac linearity performance while enabling mix-
mode operation.
3. A dual-port, double data rate, LVDS interface supports the
maximum conversion rate of 2500 MSPS.
4. On-chip controllers manage external and internal clock
domain skews.
5. Programmable differential current output with an 8.66 mA
to 31.66 mA range.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011-2012 Analog Devices, Inc. All rights reserved.




AD9737A pdf, 반도체, 판매, 대치품
AD9737A/AD9739A
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA.
Table 1.
Parameter
RESOLUTION
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUTS
Gain Error (with Internal Reference)
Full-Scale Output Current
Output Compliance Range
Common-Mode Output Resistance
Differential Output Resistance
Output Capacitance
DAC CLOCK INPUT (DACCLK_P, DACCLK_N)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Clock Rate
TEMPERATURE DRIFT
Gain
Reference Voltage
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
VDDA
VDDC
DIGITAL SUPPLY VOLTAGES
VDD33
VDD
SUPPLY CURRENTS AND POWER DISSIPATION, 2.0 GSPS
IVDDA
IVDDC
IVDD33
IVDD
Power Dissipation
Sleep Mode, IVDDA
Power-Down Mode (All Power-Down Bits Set in Register 0x01 and
Register 0x02)
IVDDA
IVDDC
IVDD33
IVDD
SUPPLY CURRENTS AND POWER DISSIPATION, 2.5 GSPS
IVDDC
IVDD33
IVDD
Power Dissipation
AD9737A
Min Typ Max
11
AD9739A
Min Typ Max
14
Unit
Bits
±0.5 ±2.5 LSB
±0.5 ±2.0 LSB
5.5 5.5 %
8.66 20.2 31.66 8.66 20.2 31.66 mA
−1.0 +1.0 −1.0 +1.0 V
10 10 MΩ
70 70 Ω
1 1 pF
1.2 1.6 2.0 1.2 1.6 2.0 V
900 900 mV
1.6 2.5 1.6 2.5 GHz
60 60 ppm/°C
20 20 ppm/°C
1.15 1.2
5
1.25 1.15 1.2
5
1.25 V
kΩ
3.1 3.3
1.70 1.8
3.5 3.1 3.3
1.90 1.70 1.8
3.5 V
1.90 V
3.10 3.3
1.70 1.8
3.5 3.10 3.3
1.90 1.70 1.8
3.5 V
1.90 V
37
158
14.5
173
0.770
2.5
38
167
16
183
2.75
37
158
14.5
173
0.770
2.5
38
167
16
183
2.75
mA
mA
mA
mA
W
mA
0.02
6
0.6
0.1
223
14.5
215
0.960
0.02
6
0.6
0.1
223
14.5
215
0.960
mA
mA
mA
mA
mA
mA
mA
mW
Rev.C | Page 4 of 64

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AD9737A 전자부품, 판매, 대치품
Data Sheet
AD9737A/AD9739A
AC SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA, fDAC = 2400 MSPS, unless otherwise noted.
Table 4.
Parameter
DYNAMIC PERFORMANCE
DAC Clock Rate
Adjusted DAC Update Rate1
Output Settling Time to 0.1%
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fOUT = 100 MHz
fOUT = 350 MHz
fOUT = 550 MHz
fOUT = 950 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD),
fOUT2 = fOUT1 + 1.25 MHz
fOUT = 100 MHz
fOUT = 350 MHz
fOUT = 550 MHz
fOUT = 950 MHz
NOISE SPECTRAL DENSITY (NSD), 0 dBFS SINGLE TONE
fOUT = 100 MHz
fOUT = 350 MHz
fOUT = 550 MHz
fOUT = 850 MHz
WCDMA ACLR (SINGLE CARRIER), ADJACENT/ALTERNATE
ADJACENT CHANNEL
fDAC = 2457.6 MSPS, fOUT = 350 MHz
fDAC = 2457.6 MSPS, fOUT = 950 MHz
fDAC = 2457.6 MSPS, fOUT = 1700 MHz (Mix-Mode)
fDAC = 2457.6 MSPS, fOUT = 2100 MHz (Mix-Mode)
Min
1600
1600
AD9737A
Typ Max
2500
2500
13
70
65
58
55
94
78
72
68
−162
−162
−161
−161
80/81
75/75
69/71
66/67
Min
1600
1600
AD9739A
Typ Max
2500
2500
13
70
65
58
55
94
78
72
68
−167
−166
−164
−163
80/80
78/79
74/74
69/72
Unit
MSPS
MSPS
ns
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBc
dBc
dBc
dBc
1 Adjusted DAC updated rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9737A/AD9739A, the minimum interpolation factor
is 1. Thus, with fDAC = 2500 MSPS, fDAC, adjusted, = 2500 MSPS.
Rev.C | Page 7 of 64

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