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부품번호 AD9741 기능
기능 250 MSPS Digital-to-Analog Converters
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AD9741 데이터시트, 핀배열, 회로
Data Sheet
Dual 8-/10-/12-/14-/16-Bit
250 MSPS Digital-to-Analog Converters
AD9741
FEATURES
High dynamic range, dual DACs
Low noise and intermodulation distortion
Single carrier WCDMA ACLR = 80 dBc at 61.44 MHz IF
Innovative switching output stage permits useable outputs
beyond Nyquist frequency
LVCMOS inputs with dual-port or optional interleaved
single-port operation
Differential analog current outputs are programmable from
8.6 mA to 31.7 mA full scale
Auxiliary 10-bit current DACs with source/sink capability for
external offset nulling
Internal 1.2 V precision reference voltage source
Operates from 1.8 V and 3.3 V supplies
315 mW power dissipation
Small footprint, Pb-free, 72-pin LFCSP
APPLICATIONS
Wireless infrastructure:
WCDMA, CDMA2000, TD-SCDMA, WiMAX
Wideband communications:
LMDS/MMDS, point-to-point
Instrumentation:
RF signal generators, arbitrary waveform generators
GENERAL DESCRIPTION
The AD9741/AD9743/AD9745/AD9746/AD9747 are pin-
compatible, high dynamic range, dual digital-to-analog
converters (DACs) with 8-/10-/12-/ 14-/16-bit resolutions
and sample rates of up to 250 MSPS. The devices include
specific features for direct conversion transmit applications,
including gain and offset compensation, and they interface
seamlessly with analog quadrature modulators, such as the
ADL5370.
A proprietary, dynamic output architecture permits synthesis
of analog outputs even above Nyquist by shifting energy away
from the fundamental and into the image frequency.
Full programmability is provided through a serial peripheral
interface (SPI) port. In addition, some pin-programmable
features are offered for those applications without a controller.
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) enables
high quality synthesis of wideband signals.
2. Proprietary switching output for enhanced dynamic
performance.
3. Programmable current outputs and dual auxiliary DACs
provide flexibility and system enhancements.
FUNCTIONAL BLOCK DIAGRAM
CLKP
CLKN
PID<15:0>
CMOS
INTERFACE
INTERFACE LOGIC
10
P2D<15:0>
SERIAL
PERIPHERAL
INTERFACE
INTERNAL
REFERENCE
AND
BIAS
GAIN
DAC
GAIN
DAC
OFFSET
DAC
OFFSET
DAC
16-BIT
DAC1
16-BIT
DAC2
IOUT1P
IOUT1N
IOUT2P
IOUT2N
AUX1P
AUX1N
AUX2P
AUX2N
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD9741 pdf, 반도체, 판매, 대치품
AD9741
Data Sheet
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum
sample rate, unless otherwise noted. The AD9745 is repeated in Table 2 so the user can compare it with all other parts.
Table 2. AD9745, AD9746, and AD9747
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Offset Error
Offset Error Temperature Coefficient
Gain Error
Gain Error Temperature Coefficient
Gain Matching (DAC1 to DAC2)
Full-Scale Output Current
Output Compliance Voltage
Output Resistance
AUXILIARY DAC OUTPUTS
Resolution
Full-Scale Output Current
Output Compliance Voltage Range—Sink Current
Output Compliance Voltage Range—Source Current
Output Resistance
Monotonicity
REFERENCE INPUT/OUTPUT
Output Voltage
Output Voltage Temperature Coefficient
External Input Voltage Range
Input or Output Resistance
POWER SUPPLY VOLTAGES
AVDD33, DVDD33
CVDD18, DVDD18
POWER SUPPLY CURRENTS
IAVDD33
IDVDD33
ICVDD18
IDVDD18
POWER DISSIPATION
fDAC = 250 MSPS, fOUT = 20 MHz
DAC Outputs Disabled
Full Device Power-Down
OPERATING TEMPERATURE
AD9745
Min Typ
Max
12
±0.13
±0.25
±0.001
0.1
±2.0
100
±1.0
8.6 31.7
−1.0 +1.0
10
10
−2.0
0.8
0
1
10
+2.0
1.6
1.6
1.2
10
1.15
5
1.3
3.13 3.47
1.70 1.90
56 60
11 15
18 22
30 34
305
120
3
−40
350
+85
AD9746
Min Typ
Max
14
±0.5
±1.0
±0.001
0.1
±2.0
100
±1.0
8.6 31.7
−1.0 +1.0
10
10
−2.0
0.8
0
1
10
+2.0
1.6
1.6
1.2
10
1.15
5
1.3
3.13 3.47
1.70 1.90
56 60
12 16
18 22
31 35
310
125
3
−40
355
+85
AD9747
Min Typ
Max
16
±2.0
±4.0
±0.001
0.1
±2.0
100
±1.0
8.6 31.7
−1.0 +1.0
10
10
−2.0
0.8
0
1
10
+2.0
1.6
1.6
1.2
10
1.15
5
1.3
3.13 3.47
1.70 1.90
56 60
12 16
18 22
32 36
310
125
3
−40
355
+85
Unit
Bits
LSB
LSB
%FSR
ppm/°C
%FSR
ppm/°C
%FSR
mA
V
Bits
mA
V
V
Bits
V
ppm/°C
V
V
V
mA
mA
mA
mA
mW
mW
mW
°C
Rev. B | Page 4 of 28

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AD9741 전자부품, 판매, 대치품
Data Sheet
AD9741
DIGITAL AND TIMING SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum
sample rate, unless otherwise noted.
Table 5. AD9741/AD9743/AD9745/AD9746/AD9747
Parameter
DAC CLOCK INPUTS (CLKP, CLKN)
Differential Peak-to-Peak Voltage
Single-Ended Peak-to-Peak Voltage
Common-Mode Voltage
Input Current
Input Frequency
DATA CLOCK OUTPUT (DCO)
Output Voltage High
Output Voltage Low
Output Current
DAC Clock to Data Clock Output Delay (tDCO)
DATA PORT INPUTS
Input Voltage High
Input Voltage Low
Input Current
Data to DAC Clock Setup Time (tDBS Dual-Port Mode)
Data to DAC Clock Hold Time (tDBH Dual-Port Mode)
DAC Clock to Analog Output Data Latency (Dual-Port Mode)
Data or IQSEL Input to DAC Clock Setup Time (tDBS Single-Port Mode)
Data or IQSEL Input to DAC Clock Hold Time (tDBH Single-Port Mode)
DAC Clock to Analog Output Data Latency (Single-Port Mode)
SERIAL PERIPHERAL INTERFACE
SCLK Frequency (fSCLK)
SCLK Pulse Width High (tPWH)
SCLK Pulse Width Low (tPWL)
CSB to SCLK Setup Time (tS)
CSB to SCLK Hold Time (tH)
SDIO to SCLK Setup Time (tDS)
SDIO to SCLK Hold Time (tDH)
SCLK to SDIO/SDO Data Valid Time (tDV)
RESET Pulse Width High
WAKE-UP TIME AND OUTPUT LATENCY
From DAC Outputs Disabled
From Full Device Power-Down
DAC Clock to Analog Output Latency (Dual-Port Mode)
DAC Clock to Analog Output Latency (Single-Port Mode)
Min
400
300
2.4
2.0
2.0
400
1200
400
1200
10
10
1
0
1
0
10
Typ
800
400
2.2
200
1200
7
8
Max
1600
800
500
1
250
0.4
10
2.8
0.8
1
7
8
40
1
Unit
mV
mV
mV
μA
MHz
V
V
mA
ns
V
V
μA
ps
ps
Cycles
ps
ps
Cycles
MHz
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
Cycles
Cycles
Rev. B | Page 7 of 28

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