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AD9786 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9786은 전자 산업 및 응용 분야에서
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부품번호 AD9786 기능
기능 200 MSPS/500 MSPS TxDAC+
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AD9786 데이터시트, 핀배열, 회로
16-Bit, 200 MSPS/500 MSPS TxDAC+® with
2×/4×/8× Interpolation and Signal Processing
AD9786
FEATURES
PRODUCT HIGHLIGHTS
16-bit resolution, 200 MSPS input data rate
IMD 90 dBc @10 MHz
1. 16-bit, high speed, interpolating TxDAC+.
Noise spectral density (NSD): −164 dBm/Hz @ 10 MHz
2. 2×/4×/8× user-selectable interpolating filter. The filter
WCDMA ACLR = 80 dBc @ 40 MHz IF
eases data rate and output signal reconstruction filter
DNL = ±0.3 LSB
requirements.
INL = ±0.6 LSB
Selectable 2×/4×/8× interpolation filters
3. 200 MSPS input data rate.
Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes
Single- or dual-channel signal processing
Selectable image rejection Hilbert transform
Flexible calibration engine
4. Ultra high speed, 500 MSPS DAC conversion rate.
5. Flexible clock with single-ended or differential input.
CMOS, 1 V p-p sine wave, and LVPECL capability.
Direct IF transmission features
Serial control interface
Versatile clock and data interface
3.3 V-compatible digital interface
On-chip 1.2 V reference
80-lead, thermally enhanced, TQFP_EP package
6. Complete CMOS DAC function. It operates from a 3.1 V
to 3.5 V single analog (AVDD) supply, 2.5 V digital supply,
and a 3.3 V digital (DRVDD) supply. The DAC full-scale
current can be reduced for lower power operation, and
a sleep mode is provided for low power idle periods.
7. On-chip voltage reference. The AD9786 includes a
APPLICATIONS
1.20 V temperature-compensated band gap voltage
Base stations: multicarrier WCDMA, GSM/EDGE, TD-SCDMA,
IS136, TETRA
Instrumentation
RF signal generators, arbitrary waveform generators
HDTV transmitters
Broadband wireless systems
reference.
8. Multichip synchronization. Multiple AD9786 DACs can
be synchronized to a single master AD9786 to ease timing
design requirements and optimize image reject transmit
performance.
Digital radio links
Satellite systems
FUNCTIONAL BLOCK DIAGRAM
P1B[15:0]
P2B[15:0]
DATACLK
LATCH
×1
LATCH
2× 2×
I
fDAC/2
fDAC/4
fDAC/8
0
90
Q
2× 2×
0
90
0
90
Δt
ZERO
STUFF
16-BIT DAC
HILBERT
FSADJ
REFIO
IOUTA
IOUTB
SDIO
SDO
CSB
SCLK
RESET
CLK+
CLK–
CLOCK DISTRIBUTION AND CONTROL
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.




AD9786 pdf, 반도체, 판매, 대치품
REVISION HISTORY
10/05—Rev. A to Rev. B
Updated Format.................................................................. Universal
Changes to Figure 1...........................................................................1
Changes to Table 2 ............................................................................6
Changes to Table 3 ............................................................................7
Changes to External Sync Mode Section .....................................31
Updated Outline Dimensions........................................................58
Changes to Ordering Guide...........................................................58
2/05—Rev. 0 to Rev. A
Changed DRVDD Supply Range...................................... Universal
Changes to DC Specifications .........................................................4
Changes to Dynamic Specifications ...............................................5
Changes to Digital Specifications....................................................6
Changes to Absolute Maximum Ratings........................................7
Change to Figure 2 ............................................................................8
Replaced Figure 13 ..........................................................................14
Replaced Figure 14 ..........................................................................14
Replaced Figure 16 ..........................................................................15
Replaced Figure 21 ..........................................................................16
Replaced Figure 22 ..........................................................................16
AD9786
Replaced Figure 26..........................................................................16
Replaced Figure 27..........................................................................17
Changes to Table 15 ........................................................................22
Change to Figure 44........................................................................26
Replaced Figure 45..........................................................................26
Change to Figure 47........................................................................27
Change to Figure 48........................................................................27
Change to Figure 51........................................................................29
Change to Figure 52........................................................................29
Change to Figure 53........................................................................30
Change to DATAADJUST Synchronization Section..................31
Changes to Power Dissipation Section.........................................40
Changes to Table 37 ........................................................................42
Changes to Data Inputs Section ....................................................46
Change to Figure 88........................................................................49
Replaced Figure 95..........................................................................55
Updated Outline Dimensions........................................................60
Changes to Ordering Guide...........................................................60
7/04—Revision 0: Initial Version
Rev. B | Page 3 of 56

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AD9786 전자부품, 판매, 대치품
AD9786
DYNAMIC SPECIFICATIONS
TMIN to TMAX; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; IOUTFS = 20 mA; differential transformer
coupled output; 50 Ω doubly terminated, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Minimum DAC Output Update Rate
Maximum DAC Output Update Rate (fDAC)
AC LINEARITY/BASEBAND MODE
Spurious-Free Dynamic Range (SFDR) to Nyquist (fOUT = 0 dBFS)
fDATA = 100 MSPS; fOUT = 5 MHz, 4×, 2× Interpolation
fDATA = 200 MSPS; fOUT = 10 MHz
fDATA = 200 MSPS; fOUT = 25 MHz
fDATA = 200 MSPS; fOUT = 50 MHz
Two-Tone Intermodulation (IMD) to Nyquist (fOUT1 = fOUT2 = –6 dBFS)
fDATA = 200 MSPS; fOUT1 = 5 MHz; fOUT2 = 6 MHz
fDATA = 200 MSPS; fOUT1 = 15 MHz; fOUT2 = 16 MHz
fDATA = 200 MSPS; fOUT1 = 25 MHz; fOUT2 = 26 MHz
fDATA = 200 MSPS; fOUT1 = 45 MHz; fOUT2 = 46 MHz
fDATA = 200 MSPS; fOUT1 = 65 MHz; fOUT2 = 66 MHz
fDATA = 200 MSPS; fOUT1 = 85 MHz; fOUT2 = 86 MHz
Noise Power Spectral Density (NPSD)
fDATA = 156 MSPS; fOUT = 10 MHz; 0 dBFS, 8 Tones, Separation = 500 kHz
fDATA = 156 MSPS; fOUT = 50 MHz; 0 dBFS, 8 Tones, Separation = 500 kHz
Adjacent Channel Power Ratio (ACLR)
WCDMA ACLR with 3.84 MHz BW, Single Carrier
IF = 21 MHz, fDATA = 122.88 MSPS, 4× Interpolation
IF = 224.76 MHz, fDATA = 122.88 MSPS, 4× Interpolation, High-Pass Interpolation Filter Mode
Min
500
Typ Max
20
93
85
78
78
85
85
84
80
78
75
−164
−161
80
72
Unit
MHz
MSPS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm/Hz
dBm/Hz
dB
dB
Rev. B | Page 6 of 56

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