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AD9516-0 데이터시트 PDF




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부품번호 AD9516-0 기능
기능 14-Output Clock Generator
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AD9516-0 데이터시트, 핀배열, 회로
Data Sheet
FEATURES
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 2.55 GHz to 2.95 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Automatic revertive and manual reference
switchover/holdover modes
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
6 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse
phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of <10 ps
4 pairs of 800 MHz LVDS clock outputs
Each output pair shares two cascaded 1-to-32 dividers
with coarse phase delay
Additive output jitter: 275 fs rms
Fine delay adjust (Δt) on each LVDS output
Each LVDS output can be reconfigured as two 250 MHz
CMOS outputs
Automatic synchronization of all outputs on power-up
Manual output synchronization available
64-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
10/40/100 Gb/sec networking line cards, including SONET,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
GENERAL DESCRIPTION
The AD9516-01 provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 2.55 GHz
to 2.95 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz
can be used.
The AD9516-0 emphasizes low jitter and phase noise to
maximize data converter performance, and it can benefit other
applications with demanding phase noise and jitter requirements.
14-Output Clock Generator with
Integrated 2.8 GHz VCO
AD9516-0
FUNCTIONAL BLOCK DIAGRAM
CP LF
REFIN
REF1
REF2
STATUS
MONITOR
VCO
CLK
DIVIDER
AND MUXs
DIV/Φ
LVPECL
DIV/Φ
LVPECL
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
LVPECL
Δt
Δt
LVDS/CMOS
Δt
Δt
LVDS/CMOS
SERIAL CONTROL PORT
AND
DIGITAL LOGIC
AD9516-0
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
Figure 1.
The AD9516-0 features six LVPECL outputs (in three pairs)
and four LVDS outputs (in two pairs). Each LVDS output can
be reconfigured as two CMOS outputs. The LVPECL outputs
operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and
the CMOS outputs operate to 250 MHz.
Each pair of outputs has dividers that allow both the divide
ratio and coarse delay (or phase) to be set. The range of division
for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs
allow a range of divisions up to a maximum of 1024.
The AD9516-0 is available in a 64-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated
by connecting the charge pump supply (VCP) to 5 V. A separate
LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The AD9516-0 is specified for operation over the industrial
range of −40°C to +85°C.
1 AD9516 is used throughout to refer to all the members of the AD9516
family. However, when AD9516-0 is used, it refers to that specific member
of the AD9516 family.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD9516-0 pdf, 반도체, 판매, 대치품
Data Sheet
REVISION HISTORY
2/13—Rev. B to Rev. C
Changes to Register 0x140 to Register 0x143 Default Values;
Table 52.............................................................................................56
Changes to Register 0x140 to Register 0x143 Default Values;
Table 57.............................................................................................71
Updated Outline Dimensions........................................................80
1/12—Rev. A to Rev. B
Changes to 0x232 Description Column, Table 62 ......................76
12/10—Rev. 0 to Rev. A
Changes to Features, Applications, and General Description..... 1
Change to CPRSET Pin Resistor Parameter in Table 1 ................ 4
Change to P = 2 DM (2/3) Parameter in Table 2 .......................... 5
Changes to Table 4 ............................................................................ 6
Changes to VCP Supply Parameter in Table 17.............................14
Change to θJA Value and Endnote in Table 19 .............................16
Added Exposed Paddle Notation to Figure 6; Changes to
Table 20.............................................................................................17
Added Figure 41; Renumbered Sequentially ...............................24
Change to High Frequency Clock Distribution—CLK or
External VCO > 1600 MHz Section; Change to Table 22..........27
Changes to Table 24 ........................................................................29
Change to Configuration and Register Settings Section............31
Change to Phase Frequency Detector (PFD) Section ................32
Changes to Charge Pump (CP), On-Chip VCO, PLL
External Loop Filter, and PLL Reference Inputs Sections .........33
Change to Figure 47; Added Figure 48.........................................33
AD9516-0
Changes to Reference Switchover and VCXO/VCO
Feedback Divider N—P, A, B, R Sections .................................... 34
Changes to Table 28 ........................................................................ 35
Change to Holdover Section.......................................................... 37
Changes to VCO Calibration Section........................................... 39
Changes to Clock Distribution Section........................................ 40
Added Endnote to Table 34 ........................................................... 41
Changes to Channel Dividers—LVDS/CMOS Outputs
Section; Added Endnote to Table 39 ............................................ 43
Changes to Write Section............................................................... 50
Change to the Instruction Word (16 Bits) Section ..................... 51
Change to Figure 65........................................................................ 52
Added Thermal Performance Section.......................................... 54
Changes to Register Address 0x003 in Table 52.......................... 55
Changes to Table 53 ........................................................................ 59
Changes to Table 54 ........................................................................ 60
Changes to Table 55 ........................................................................ 66
Changes to Table 56 ........................................................................ 68
Changes to Table 57 ........................................................................ 71
Changes to Table 58 ........................................................................ 73
Changes to Table 59 ........................................................................ 74
Changes to Table 60 and Table 61 ................................................. 76
Added Frequency Planning Using the AD9516 Section............ 77
Changes to Figure 71 and Figure 73; Added Figure 72.............. 78
Changes to LVPECL Clock Distribution and LVDS Clock
Distribution Sections ...................................................................... 78
Updated Outline Dimensions........................................................80
4/07—Revision 0: Initial Version
Rev. C | Page 3 of 80

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AD9516-0 전자부품, 판매, 대치품
AD9516-0
Data Sheet
CLOCK INPUTS
Table 3.
Parameter
Min Typ Max Unit Test Conditions/Comments
CLOCK INPUTS (CLK, CLK)
Differential input
Input Frequency
01 2.4 GHz High frequency distribution (VCO divider)
01 1.6 GHz Distribution only (VCO divider bypassed)
Input Sensitivity, Differential
150 mV p-p Measured at 2.4 GHz; jitter performance is improved
with slew rates > 1 V/ns
Input Level, Differential
2 V p-p Larger voltage swings may turn on the protection
diodes and may degrade jitter performance
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
1.3
1.3
1.57 1.8
1.8
150
V
V
mV p-p
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK ac-bypassed to RF ground
Input Resistance
3.9 4.7 5.7 kΩ Self-biased
Input Capacitance
2 pF
1 Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
CLOCK OUTPUTS
Table 4.
Parameter
Min Typ Max Unit
LVPECL CLOCK OUTPUTS
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5
Output Frequency, Maximum
2950
MHz
Output High Voltage (VOH)
Output Low Voltage (VOL)
Output Differential Voltage (VOD)
VS − 1.12
VS − 2.03
550
VS − 0.98
VS − 1.77
790
VS − 0.84
VS − 1.49
980
V
V
mV
LVDS CLOCK OUTPUTS
OUT6, OUT7, OUT8, OUT9
Output Frequency
800 MHz
Differential Output Voltage (VOD)
247
360
454
mV
Delta VOD
Output Offset Voltage (VOS)
Delta VOS
1.125
1.24
Short-Circuit Current (ISA, ISB)
CMOS CLOCK OUTPUTS
OUT6A, OUT6B, OUT7A, OUT7B,
OUT8A, OUT8B, OUT9A, OUT9B
Output Frequency
Output Voltage High (VOH)
Output Voltage Low (VOL)
14
VS − 0.1
25 mV
1.375
25
V
mV
24 mA
250 MHz
V
0.1 V
Test Conditions/Comments
Termination = 50 Ω to VS − 2 V
Differential (OUT, OUT)
Using direct to output; see Figure 25 for peak-to –
peak differential amplitude
VOH − VOL for each leg of a differential pair for default
amplitude setting with driver not toggling; see
Figure 25 for variation over frequency
Differential termination 100 Ω at 3.5 mA
Differential (OUT, OUT)
The AD9516 outputs toggle at higher frequencies,
but the output amplitude may not meet the VOD
specification; see Figure 26
VOH − VOL measurement across a differential pair at
the default amplitude setting with output driver
not toggling; see Figure 26 for variation over
frequency
This is the absolute value of the difference between
VOD when the normal output is high vs. when the
complementary output is high
(VOH + VOL)/2 across a differential pair
This is the absolute value of the difference between
VOS when the normal output is high vs. when the
complementary output is high
Output shorted to GND
Single-ended; termination = 10 pF
See Figure 27
At 1 mA load
At 1 mA load
Rev. C | Page 6 of 80

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