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AD9516-3 데이터시트 PDF




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부품번호 AD9516-3 기능
기능 14-Output Clock Generator
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AD9516-3 데이터시트, 핀배열, 회로
Data Sheet
14-Output Clock Generator with
Integrated 2.0 GHz VCO
AD9516-3
FEATURES
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 1.75 GHz to 2.25 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Automatic revertive and manual reference
switchover/holdover modes
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
6 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse
phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of <10 ps
4 pairs of 800 MHz LVDS clock outputs
Each output pair shares two cascaded 1-to-32 dividers
with coarse phase delay
Additive output jitter: 275 fs rms
Fine delay adjust (Δt) on each LVDS output
Each LVDS output can be reconfigured as two 250 MHz
CMOS outputs
Automatic synchronization of all outputs on power-up
Manual output synchronization available
64-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
10/40/100 Gb/sec networking line cards, including SONET,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
GENERAL DESCRIPTION
The AD9516-31 provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an on-
chip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to
2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz
can be used.
The AD9516-3 emphasizes low jitter and phase noise to
maximize data converter performance, and it can benefit other
applications with demanding phase noise and jitter requirements.
FUNCTIONAL BLOCK DIAGRAM
CP LF
REFIN
REF1
REF2
STATUS
MONITOR
VCO
CLK
DIVIDER
AND MUXs
DIV/Φ
LVPECL
DIV/Φ
LVPECL
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
LVPECL
Δt
Δt
LVDS/CMOS
Δt
Δt
LVDS/CMOS
SERIAL CONTROL PORT
AND
DIGITAL LOGIC
AD9516-3
Figure 1.
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
The AD9516-3 features six LVPECL outputs (in three pairs)
and four LVDS outputs (in two pairs). Each LVDS output can
be reconfigured as two CMOS outputs. The LVPECL outputs
operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and
the CMOS outputs operate to 250 MHz.
Each pair of outputs has dividers that allow both the divide
ratio and coarse delay (or phase) to be set. The range of division
for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs
allow a range of divisions up to a maximum of 1024.
The AD9516-3 is available in a 64-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated
by connecting the charge pump supply (VCP) to 5 V. A separate
LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The AD9516-3 is specified for operation over the standard
industrial range of −40°C to +85°C.
1 AD9516 is used throughout to refer to all the members of the AD9516 family.
However, when AD9516-3 is used, it refers to that specific member of the
AD9516 family.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD9516-3 pdf, 반도체, 판매, 대치품
AD9516-3
Data Sheet
SPECIFICATIONS
Typical is given for VS = VS_LVPECL = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted.
Minimum and maximum values are given over full VS and TA (−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
VS
VS_LVPECL
VCP
RSET Pin Resistor
CPRSET Pin Resistor
BYPASS Pin Capacitor
Min
3.135
2.375
VS
2.7
Typ
3.3
4.12
5.1
Max
3.465
VS
5.25
10
Unit
V
V
V
kΩ
kΩ
220 nF
Test Conditions/Comments
3.3 V ± 5%
Nominally 2.5 V to 3.3 V ± 5%
Nominally 3.3 V to 5.0 V ± 5%
Sets internal biasing currents; connect to ground
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 µA);
actual current can be calculated by: CP_lsb = 3.06/CPRSET; connect
to ground
Bypass for internal LDO regulator; necessary for LDO stability;
connect to ground
PLL CHARACTERISTICS
Table 2.
Parameter
VCO (ON-CHIP)
Frequency Range
VCO Gain (KVCO)
Tuning Voltage (VT)
Frequency Pushing (Open-Loop)
Phase Noise at 100 kHz Offset
Phase Noise at 1 MHz Offset
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Input Frequency
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Dual Single-Ended Mode (REF1, REF2)
Input Frequency (AC-Coupled)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled)
Input Logic High
Input Logic Low
Input Current
Input Capacitance
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
Antibacklash Pulse Width
Min Typ Max Unit Test Conditions/Comments
1750
0.5
50
1
−108
−126
2250
VCP
0.5
MHz
MHz/V
V
MHz/V
dBc/Hz
dBc/Hz
See Figure 15
See Figure 10
VCP ≤ VS when using internal VCO; outside of this range, the CP
spurs may increase due to CP up/down mismatch
f = 2000 MHz
f = 2000 MHz
0
250
1.35 1.60
1.30 1.50
4.0 4.8
4.4 5.3
20
0
0.8
2.0
−100
2
250
1.75
1.60
5.9
6.4
250
250
0.8
+100
MHz
mV p-p
V
V
kΩ
kΩ
MHz
MHz
V p-p
V
V
µA
pF
Differential mode (can accommodate single-ended input by
ac grounding undriven input)
Frequencies below about 1 MHz should be dc-coupled; be careful
to match VCM (self-bias voltage)
PLL figure of merit (FOM) increases with increasing slew rate; see
Figure 14
Self-bias voltage of REFIN1
Self-bias voltage of REFIN1
Self-biased1
Self-biased1
Two single-ended CMOS-compatible inputs
Slew rate > 50 V/µs
Slew rate > 50 V/µs; CMOS levels
Should not exceed VS p-p
Each pin, REFIN/REFIN (REF1/REF2)
100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns
45 MHz Antibacklash pulse width = 6.0 ns
1.3 ns Register 0x017[1:0] = 01b
2.9 ns Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b
6.0 ns Register 0x017[1:0] = 10b
Rev. C | Page 4 of 80

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AD9516-3 전자부품, 판매, 대치품
Data Sheet
AD9516-3
TIMING CHARACTERISTICS
Table 5.
Parameter
Min Typ Max Unit Test Conditions/Comments
LVPECL
Output Rise Time, tRP
Output Fall Time, tFP
Termination = 50 Ω to VS − 2 V; level = 810 mV
70 180 ps 20% to 80%, measured differentially
70 180 ps 80% to 20%, measured differentially
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUTPUT
High Frequency Clock Distribution Configuration 835 995
1180 ps
See Figure 43
Clock Distribution Configuration
773 933 1090 ps
See Figure 45
Variation with Temperature
0.8 ps/°C
OUTPUT SKEW, LVPECL OUTPUTS1
LVPECL Outputs That Share the Same Divider
5 15 ps
LVPECL Outputs on Different Dividers
13 40 ps
All LVPECL Outputs Across Multiple Parts
220 ps
LVDS
Termination = 100 Ω differential; 3.5 mA
Output Rise Time, tRL
Output Fall Time, tFL
170 350 ps
160 350 ps
20% to 80%, measured differentially2
20% to 80%, measured differentially2
PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUTPUT
OUT6, OUT7, OUT8, OUT9
Delay off on all outputs
For All Divide Values
1.4 1.8 2.1 ns
Variation with Temperature
1.25 ps/°C
OUTPUT SKEW, LVDS OUTPUTS1
Delay off on all outputs
LVDS Outputs That Share the Same Divider
6 62 ps
LVDS Outputs on Different Dividers
25 150 ps
All LVDS Outputs Across Multiple Parts
430 ps
CMOS
Termination = open
Output Rise Time, tRC
Output Fall Time, tFC
495 1000 ps
475 985 ps
20% to 80%; CLOAD = 10 pF
80% to 20%; CLOAD = 10 pF
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUTPUT
For All Divide Values
1.6
2.1
2.6 ns
Fine delay off
Variation with Temperature
2.6 ps/°C
OUTPUT SKEW, CMOS OUTPUTS1
Fine delay off
CMOS Outputs That Share the Same Divider
4 66 ps
All CMOS Outputs on Different Dividers
28 180 ps
All CMOS Outputs Across Multiple Parts
675 ps
DELAY ADJUST3
LVDS and CMOS
Shortest Delay Range4
Register 0xA1 (0xA4, 0xA7, 0xAA), Bits[5:0] = 101111b
Zero Scale
50 315 680 ps
Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 000000b
Full Scale
540 880 1180 ps
Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 101111b
Longest Delay Range4
Register 0xA1 (0xA4, 0xA7, 0xAA), Bits[5:0] = 000000b
Zero Scale
200 570 950 ps
Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 000000b
Quarter Scale
1.72 2.31 2.89 ns
Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 001100b
Full Scale
5.7 8.0 10.1 ns
Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 101111b
Delay Variation with Temperature
Short Delay Range5
Zero Scale
0.23 ps/°C
Full Scale
−0.02
ps/°C
Long Delay Range5
Zero Scale
0.3 ps/°C
Full Scale
0.24 ps/°C
1 This is the difference between any two similar delay paths while operating at the same voltage and temperature.
2 Corresponding CMOS drivers set to A for noninverting and B for inverting.
3 The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output.
4 Incremental delay; does not include propagation delay.
5 All delays between zero scale and full scale can be estimated by linear interpolation.
Rev. C | Page 7 of 80

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