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AD9520-3 데이터시트 PDF




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부품번호 AD9520-3 기능
기능 12 LVPECL/24 CMOS Output Clock Generator
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AD9520-3 데이터시트, 핀배열, 회로
Data Sheet
12 LVPECL/24 CMOS Output Clock
Generator with Integrated 2 GHz VCO
AD9520-3
FEATURES
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 1.72 GHz to 2.25 GHz
Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz
1 differential or 2 single-ended reference inputs
Accepts CMOS, LVDS, or LVPECL references to 250 MHz
Accepts 16.62 MHz to 33.3 MHz crystal for reference input
Optional reference clock doubler
Reference monitoring capability
Automatic/manual reference holdover and reference
switchover modes, with revertive switching
Glitch-free switchover between references
Automatic recovery from holdover
Digital or analog lock detect, selectable
Optional zero delay operation
Twelve 1.6 GHz LVPECL outputs divided into 4 groups
Each group of 3 outputs shares a 1-to-32 divider with
phase delay
Additive output jitter as low as 225 fs rms
Channel-to-channel skew grouped outputs < 16 ps
Each LVPECL output can be configured as 2 CMOS outputs
(for fOUT ≤ 250 MHz)
Automatic synchronization of all outputs on power-up
Manual output synchronization available
SPI- and I²C-compatible serial control port
64-lead LFCSP
Nonvolatile EEPROM stores configuration settings
APPLICATIONS
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10GFC,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures
GENERAL DESCRIPTION
The AD9520-31 provides a multioutput clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 1.72 GHz
to 2.25 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz
can also be used.
FUNCTIONAL BLOCK DIAGRAM
CP LF
OPTIONAL
REFIN
REFIN
CLK
REF1
REF2
STATUS
MONITOR
VCO
DIVIDER
AND MUXES
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
ZERO
DELAY
LVPECL/
CMOS
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
SPI/I2C CONTROL
PORT AND
EEPROM
DIGITAL LOGIC
AD9520
Figure 1.
The AD9520-3 serial interface supports both SPI and I²C ports.
An in-package EEPROM, which can be programmed through the
serial interface, can store user-defined register settings for
power-up and chip reset.
The features 12 LVPECL outputs in four groups. Any of the 1.6
GHz LVPECL outputs can be reconfigured as two 250 MHz
CMOS outputs. If an application requires LVDS drivers instead
of LVPECL drivers, refer to the AD9522-3.
Each group of three outputs has a divider that allows both the
divide ratio (from 1 to 32) and the phase offset or coarse time
delay to be set.
The is available in a 64-lead LFCSP and can be operated from a
single 3.3 V supply. The external VCO can have an operating
voltage of up to 5.5 V. A separate output driver power supply
can be from 2.375 V to 3.465 V.
The AD9520-3 is specified for operation over the standard
industrial range of −40°C to +85°C.
1 AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-3 is used, it refers to that specific member of the
AD9520 family.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD9520-3 pdf, 반도체, 판매, 대치품
AD9520-3
Data Sheet
SPECIFICATIONS
Typical is given for VS = VS_DRV = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. Minimum
and maximum values are given over full VS and TA (−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
POWER PINS
VS
VS_DRV
VCP
CURRENT SET RESISTORS
RSET Pin Resistor
CPRSET Pin Resistor
Min
3.135
2.375
VS
Typ
3.3
4.12
5.1
BYPASS PIN CAPACITOR
PLL CHARACTERISTICS
220
Max Unit
3.465
VS
5.25
V
V
V
kΩ
kΩ
nF
Test Conditions/Comments
3.3 V ± 5%
Nominally 2.5 V to 3.3 V ± 5%
Nominally 3.3 V to 5.0 V ± 5%
Sets internal biasing currents; connect to ground
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 µA); actual
current can be calculated by CP_lsb = 3.06/CPRSET; connect to ground
Bypass for internal LDO regulator; necessary for LDO stability; connect to ground
Table 2.
Parameter
VCO (ON CHIP)
Frequency Range
VCO Gain (KVCO)
Tuning Voltage (VT)
Frequency Pushing (Open-Loop)
Phase Noise at 1 kHz Offset
Phase Noise at 100 kHz Offset
Phase Noise at 1 MHz Offset
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Input Frequency
Input Sensitivity
Min
1720
0.5
0
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Dual Single-Ended Mode (REF1, REF2)
Input Frequency (AC-Coupled) with DC
Offset Off)
Input Frequency (AC-Coupled with
DC Offset On)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled with
DC Offset Off)
Input Sensitivity (AC-Coupled with
DC Offset On)
Input Logic High, DC Offset Off
Input Logic Low, DC Offset Off
Input Current
Input Capacitance
Pulse Width High/Low
1.35
1.30
4.0
4.4
10
0
0.55
1.5
2.0
−100
1.8
Typ Max
Unit Test Conditions/Comments
47
1
−55
−110
−129
2250
VCP − 0.5
MHz
MHz/V
V
MHz/V
dBc/Hz
dBc/Hz
dBc/Hz
See Figure 8
VT ≤ VS when using internal VCO
f = 2000 MHz
f = 2000 MHz
f = 2000 MHz
250
280
1.60 1.75
1.50 1.60
4.8 5.9
5.3 6.4
250
MHz
mV p-p
V
V
kΩ
kΩ
MHz
Differential mode (can accommodate single-ended
input by ac grounding undriven input)
Frequencies below about 1 MHz should be dc-coupled;
be careful to match VCM (self-bias voltage)
PLL figure of merit (FOM) increases with increasing slew
rate (see Figure 12); the input sensitivity is sufficient for
ac-coupled LVDS and LVPECL signals
Self-bias voltage of REFIN1
Self-bias voltage of REFIN1
Self-biased1
Self-biased1
Two single-ended CMOS-compatible inputs
Slew rate must be >50 V/µs
250 MHz Slew rate must be >50 V/µs, and input amplitude
sensitivity specification must be met; see the input
sensitivity parameter
250 MHz Slew rate > 50 V/µs; CMOS levels
3.28
V p-p
VIH should not exceed VS
2.78
V p-p
VIH should not exceed VS
V
0.8 V
+100
µA
2 pF
ns
Rev. B | Page 4 of 80
Each pin, REFIN (REF1)/REFIN (REF2)
The amount of time that a square wave is high/low;
determines the allowable input duty cycle

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AD9520-3 전자부품, 판매, 대치품
Data Sheet
AD9520-3
CLOCK INPUTS
Table 3.
Parameter
CLOCK INPUTS (CLK, CLK)
Input Frequency
Min Typ Max
01 2.4
01 2.0
Input Sensitivity, Differential
01
1.6
150
Input Level, Differential
2
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
1.3
1.3
3.9
1.57 1.8
1.8
150
4.7 5.7
2
1 Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
Unit
GHz
GHz
GHz
mV p-p
V p-p
V
V
mV p-p
kΩ
pF
Test Conditions/Comments
Differential input
High frequency distribution (VCO divider)
Distribution only (VCO divider bypassed); this is the
frequency range supported by the channel divider for
all divide ratios except divide-by-17 and divide-by-3
Distribution only (VCO divider bypassed); this is the
frequency range supported by all channel divider ratios
Measured at 2.4 GHz; jitter performance is improved
with slew rates > 1 V/ns; the input sensitivity is
sufficient for ac-coupled LVDS and LVPECL signals
Larger voltage swings can turn on the protection
diodes and can degrade jitter performance
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK ac-bypassed to RF ground
Self-biased
CLOCK OUTPUTS
Table 4.
Parameter
LVPECL CLOCK OUTPUTS
OUT0, OUT1, OUT2, OUT3, OUT4,
OUT5, OUT6, OUT7, OUT8,
OUT9, OUT10, OUT11
Output Frequency, Maximum
Output High Voltage, VOH
Output Low Voltage, VOL
Output Differential Voltage, VOD
CMOS CLOCK OUTPUTS
OUT0A, OUT0B, OUT1A, OUT1B,
OUT2A, OUT2B, OUT3A, OUT3B,
OUT4A, OUT4B, OUT5A, OUT5B,
OUT6A, OUT6B, OUT7A, OUT7B,
OUT8A, OUT8B, OUT9A, OUT9B,
OUT10A, OUT10B, OUT11A,
OUT11B
Output Frequency
Output Voltage High, VOH
Output Voltage Low, VOL
Output Voltage High, VOH
Output Voltage Low, VOL
Output Voltage High, VOH
Output Voltage Low, VOL
Min Typ Max Unit
2400
MHz
VS_DRV − 1.07
VS_DRV − 1.95
660
VS_DRV − 0.96
VS_DRV − 1.79
820
VS_DRV − 0.84
VS_DRV − 1.64
950
V
V
mV
VS − 0.1
2.7
1.8
250 MHz
V
0.1 V
V
0.5 V
V
0.6 V
Rev. B | Page 7 of 80
Test Conditions/Comments
Termination = 50 Ω to VS_DRV − 2 V
Differential (OUT, OUT)
Using direct to output (see Figure 20); higher
frequencies are possible, but the resulting amplitude
does not meet the VOD specification; the maximum
output frequency is limited by either the maximum VCO
frequency or the frequency at the CLK inputs,
depending on the AD9520-3 configuration
VOH − VOL for each leg of a differential pair for default
amplitude setting with the driver not toggling; the
peak-to-peak amplitude measured using a differential
probe across the differential pair with the driver
toggling is roughly 2× these values (see Figure 20 for
variation over frequency)
Single-ended; termination = 10 pF
See Figure 21
1 mA load, VS_DRV = 3.3 V/2.5 V
1 mA load, VS_DRV = 3.3 V/2.5 V
10 mA load VS_DRV = 3.3 V
10 mA load, VS_DRV = 3.3 V
10 mA load, VS_DRV = 2.5 V
10 mA load, VS_DRV = 2.5 V

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