PDF AD9522-5 Data sheet ( Hoja de datos )

Número de pieza	AD9522-5
Descripción	12 LVDS/24 CMOS Output Clock Generator
Fabricantes	Analog Devices
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Data Sheet FEATURES Low phase noise, phase-locked loop (PLL) Supports external 3.3 V/5 V voltage controlled oscillator (VCO)/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs Accepts CMOS, LVPECL, or LVDS references to 250 MHz Accepts 16.62 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler Reference monitoring capability Revertive automatic and manual reference switchover/ holdover modes Glitch-free switchover between references Automatic recovery from holdover Digital or analog lock detect, selectable Optional zero delay operation Twelve 800 MHz LVDS outputs divided into 4 groups Each group of 3 has a 1-to-32 divider with phase delay Additive output jitter as low as 242 fs rms Channel-to-channel skew grouped outputs < 60 ps Each LVDS output can be configured as 2 CMOS outputs (for fOUT ≤ 250 MHz) Automatic synchronization of all outputs on power-up Manual synchronization of outputs as needed SPI- and I²C-compatible serial control port 64-lead LFCSP Nonvolatile EEPROM stores configuration settings APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures GENERAL DESCRIPTION The AD9522-51 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO. 12 LVDS/24 CMOS Output Clock Generator AD9522-5 FUNCTIONAL BLOCK DIAGRAM CP REFIN REFIN CLK REF1 STATUS MONITOR REF2 DIVIDER AND MUXES DIV/Φ DIV/Φ DIV/Φ DIV/Φ ZERO DELAY LVDS/ CMOS OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 SPI/I2C CONTROL PORT AND EEPROM DIGITAL LOGIC AD9522-5 Figure 1. The AD9522 serial interface supports both SPI and I2C® ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset. The AD9522 features 12 LVDS outputs in four groups. Any of the 800 MHz LVDS outputs can be reconfigured as two 250 MHz CMOS outputs. Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set. The AD9522 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V. The AD9522 is specified for operation over the standard industrial range of −40°C to +85°C. The AD9520-5 is an equivalent part to the AD9522-5 featuring LVPECL/CMOS drivers instead of LVDS/CMOS drivers. 1 The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-5 is used, it is referring to that specific member of the AD9522 family. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2008–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page AD9522-5 REVISION HISTORY 3/15—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Table 1 and Table 2....................................................... 5 Change to Input Frequency Parameter, Table 3 ........................... 8 Changes to Table 4............................................................................ 8 Changes to SDIO, SDO (Outputs) Parameter, Test Conditions/Comments Column, Table 10 .................................. 12 Changes to Table 14........................................................................ 14 Change to Junction Temperature Parameter, Table 16 .............. 16 Changes to Pin 22 Description Column, Table 18 ..................... 18 Changes to Figure 26...................................................................... 27 Changes to Table 22........................................................................ 28 Changes to Figure 27...................................................................... 29 Changes to Configuration of the PLL Section and Charge Pump (CP) Section .................................................................................... 30 Changes to PLL Reference Inputs Section and Reference Switchover Section ......................................................................... 31 Changes to Reference Divider R Section, Prescaler Section, A and B Counters Section, and R and N Divider Delays Section...................32 Changes to Table 25 and Current Source Digital Lock Detect (CSDLD) Section ............................................................................ 33 Changes to External VCXO/VCO Clock Input (CLK/CLK) and Holdover Section ............................................................................ 34 Changes to Frequency Status Monitors Section ......................... 36 Data Sheet Changes to Clock Distribution Section....................................... 38 Added Channel Divider Maximum Frequency Section............ 39 Changes to Duty Cycle and Duty-Cycle Correction Section ... 39 Changes to Table 31 ....................................................................... 40 Changes to Synchronizing the Outputs—SYNC Function Section.............................................................................................. 41 Changes to Power-On Reset Section, Hardware Reset via the RESET Pin Section, and Soft Reset via the Serial Port Section....... 43 Changes to Pin Descriptions Section and SPI Mode Operation Section.............................................................................................. 48 Changes to Figure 52, Figure 53 Caption, and Figure 54.......... 50 Changes to EEPROM Operation Section, Writing to EEPROM section, and Reading from EEPROM section ............................ 52 Changes to Table 43 ....................................................................... 55 Changes to Table 44 and Table 45 ................................................ 59 Changes to Table 47 ....................................................................... 61 Changes to Table 49 ....................................................................... 68 Changes to Table 52 ....................................................................... 71 Change to Frequency Planning Using the AD9522 Section..... 72 Updated Outline Dimensions....................................................... 74 12/08—Revision 0: Initial Version Rev. A \| Page 4 of 74 5 Page AD9522-5 Data Sheet CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6. Parameter CLK-TO-LVDS ADDITIVE PHASE NOISE CLK = 1.6 GHz, Output = 800 MHz Divider = 2 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 1 MHz Offset At 10 MHz Offset At 100 MHz Offset CLK = 1 GHz, Output = 200 MHz Divider = 5 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 1 MHz Offset >10 MHz Offset CLK-TO-CMOS ADDITIVE PHASE NOISE CLK = 1 GHz, Output = 500 MHz Divider = 2 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 1 MHz Offset >10 MHz Offset CLK = 1 GHz, Output = 50 MHz Divider = 20 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 1 MHz Offset >10 MHz Offset Min Typ Max Unit Test Conditions/Comments Distribution section only; does not include PLL and VCO Input slew rate > 1 V/ns −100 −110 −117 −126 −134 −137 −147 −148 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Input slew rate > 1 V/ns −111 −123 −132 −141 −146 −150 −156 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Distribution section only; does not include PLL and VCO Input slew rate > 1 V/ns −102 −114 −122 −129 −135 −140 −150 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Input slew rate > 1 V/ns −125 −136 −144 −152 −157 −160 −164 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. A \| Page 10 of 74 11 Page

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