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PDF AD9627-11 Data sheet ( Hoja de datos )
| Número de pieza | AD9627-11 | |
| Descripción | Dual Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9627-11 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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FEATURES
SNR = 65.8 dBc (66.8 dBFS) to 70 MHz @ 105 MSPS
SFDR = 85 dBc to 70 MHz @ 105 MSPS
Low power: 600 mW @ 105 MSPS
SNR = 65.7 dBc (66.7 dBFS) to 70 MHz @ 150 MSPS
SFDR = 84 dBc to 70 MHz @ 150 MSPS
Low power: 820 mW @ 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS
output supply
Integer 1-to-8 input clock divider
IF sampling frequencies to 450 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
Integrated receive features
Fast detect/threshold bits
Composite signal monitor
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
GSM, EDGE, WCDMA, CDMA2000,
WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
11-Bit, 105 MSPS/150 MSPS, 1.8 V
Dual Analog-to-Digital Converter
AD9627-11
FUNCTIONAL BLOCK DIAGRAM
SDIO/ SCLK/
AVDD DVDD FD(0:3)A DCS DFS CSB DRVDD
FD BITS/THRESHOLD
DETECT
SPI
VIN+A
VIN–A
VREF
SENSE
CML
RBIAS
SHA
REF
SELECT
ADC
PROGRAMMING DATA
SIGNAL
MONITOR
DIVIDE
1 TO 8
DUTY CYCLE
STABILIZER
DCO
GENERATION
VIN–B
VIN+B
SHA
ADC
AD9627-11
SIGNAL MONITOR
DATA
MULTICHIP FD BITS/THRESHOLD SIGNAL MONITOR
SYNC
DETECT
INTERFACE
D10A
D0A
CLK+
CLK–
DCOA
DCOB
D10B
D0B
AGND SYNC
FD(0:3)B
SMI SMI SMI DRGND
SDFS SCLK/ SDO/
NOTES
PDWN OEB
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
Figure 1.
PRODUCT HIGHLIGHTS
1. Integrated dual, 11-bit, 105 MSPS/150 MSPS ADC.
2. Fast overrange detect and signal monitor with serial output.
3. Signal monitor block with dedicated serial output mode.
4. Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 450 MHz.
5. Operation from a single 1.8 V supply and a separate digital
output driver supply to accommodate 1.8 V to 3.3 V logic
families.
6. Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, test modes, and voltage
reference mode.
7. Pin compatibility with the AD9640, AD9627, and AD9600
for a simple migration from 11 bits to 14 bits, 12 bits, or
10 bits.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
1 page  
AD9627-11
SPECIFICATIONS
ADC DC SPECIFICATIONS—AD9627-11-105/AD9627-11-150
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted.
Table 1.
AD9627-11-105
Parameter
Temperature Min
Typ
Max
RESOLUTION
Full 11
ACCURACY
No Missing Codes
Full
Guaranteed
Offset Error
Full ±0.3 ±0.7
Gain Error
Full
−3.6 −2.2
−1.0
Differential Nonlinearity (DNL)1 Full
±0.3
25°C ±0.1
Integral Nonlinearity (INL)1
Full
±0.5
25°C ±0.2
MATCHING CHARACTERISTIC
Offset Error
25°C ±0.3 ±0.7
Gain Error
25°C ±0.2 ±0.75
TEMPERATURE DRIFT
Offset Error
Full ±15
Gain Error
Full ±95
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode) Full
±5 ±16
Load Regulation @ 1.0 mA
25°C
7
INPUT REFERRED NOISE
VREF = 1.0 V
25°C 0.15
ANALOG INPUT
Input Span, VREF = 1.0 V
Full
2
Input Capacitance2
Full
8
VREF INPUT RESISTANCE
Full
6
POWER SUPPLIES
Supply Voltage
AVDD, DVDD
Full
1.7 1.8
1.9
DRVDD (CMOS Mode)
Full
1.7 3.3
3.6
DRVDD (LVDS Mode) Full 1.7 1.8 1.9
Supply Current
IAVDD1, 3
IDVDD1, 3
IDRVDD1 (3.3 V CMOS)
IDRVDD1 (1.8 V CMOS)
IDRVDD1 (1.8 V LVDS)
Full
Full
Full
Full
Full
310
34
365
34
16
44
POWER CONSUMPTION
DC Input
Full 600 650
Sine Wave Input1 (DRVDD = 1.8 V) Full
645
Sine Wave Input1 (DRVDD = 3.3 V) Full
730
Standby Power4
Full
68
Power-Down Power
Full
2.5 6
AD9627-11-150
Min Typ
Max
11
Guaranteed
±0.2 ±0.6
−4.3 −3.0
−1.7
±0.4
±0.1
±0.7
±0.3
±0.2 ±0.7
±0.2 ±0.7
±15
±95
±5 ±16
7
0.15
2
8
6
1.7 1.8
1.7 3.3
1.7 1.8
1.9
3.6
1.9
419
50
495
42
29
46
820
895
1000
77
2.5
890
6
Unit
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
% FSR
% FSR
ppm/°C
ppm/°C
mV
mV
LSB rms
V p-p
pF
kΩ
V
V
V
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure.
3 The maximum limit applies to the combination of IAVDD and IDVDD currents.
4 Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).
Rev. B | Page 5 of 72
5 Page 
AD9627-11
CLK+
CLK–
CH A/CH B DATA
N+1 N+2
N
tA
tCLK
N+3
N+4
N+5
N+6
N+7
N+8
tPD
ABABABABABABABABABA
CH A/CH B FAST
DETECT
N – 13 N – 12 N – 11 N – 10 N – 9
N–8
N–7
N–6
N–5 N–4
ABABABABABABABABABA
DCO+
N–7 N–6
N–5
N–4
N–3
tDCO
N–2
N–1
tCLK
N
N+1 N+2
DCO–
Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 001 Through Fast Detect Mode Select Bits = 100)
CLK+
CLK–
SMI SCLK
SMI SDFS
SMI SDO
CLK+
SYNC
tSSYNC
tHSYNC
Figure 4. SYNC Input Timing Requirements
tCSSCLK
tSSCLKSDFS
tSSCLKSDO
DATA
Figure 5. Signal Monitor SPORT Output Timing (Divide-by-2 Mode)
DATA
Rev. B | Page 11 of 72
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9627-11.PDF ] | |
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