PCF8577C Datasheet PDF - Philips
| Part Number | PCF8577C | |
| Description | LCD direct/duplex driver | |
| Manufacturers | Philips | |
| Logo |  |
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INTEGRATED CIRCUITS
DATA SHEET
PCF8577C
LCD direct/duplex driver with
I2C-bus interface
Product specification
Supersedes data of 1997 Mar 28
File under Integrated Circuits, IC12
1998 Jul 30
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Philips Semiconductors
LCD direct/duplex driver with
I2C-bus interface
Product specification
PCF8577C
6 FUNCTIONAL DESCRIPTION
6.1 Hardware subaddress A0, A1, A2
The hardware subaddress lines A0, A1 and A2 are used to
program the device subaddress for each PCF8577C
connected to the I2C-bus. Lines A0 and A2 are shared with
OSC and BP2 respectively to reduce pin-out
requirements.
1. Line A0 is defined as LOW (logic 0) when this pin is
used for the local oscillator or when connected to VSS.
Line A0 is defined as HIGH (logic 1) when connected
to VDD.
2. Line A1 must be defined as LOW (logic 0) or as HIGH
(logic 1) by connection to VSS or VDD respectively.
3. In the direct drive mode the second backplane signal
BP2 is not used and the A2/BP2 pin is exclusively the
A2 input. Line A2 is defined as LOW (logic 0) when
connected to VSS or, if this is not possible, by leaving
it unconnected (internal pull-down). Line A2 is defined
as HIGH (logic 1) when connected to VDD.
4. In the duplex drive mode the second backplane signal
BP2 is required and the A2 signal is undefined. In this
mode device selection is made exclusively from
lines A0 and A1.
6.2 Oscillator A0/OSC
The PCF8577C has a single-pin built-in oscillator which
provides the modulation for the LCD segment driver
outputs. One external resistor and one external capacitor
are connected to the A0/OSC pin to form the oscillator (see
Figs 15 and 16). For correct start-up of the oscillator after
power on, the resistor and capacitor must be connected to
the same VSS/VDD as the chip. In an expanded system
containing more than one PCF8577C the backplane
signals are usually common to all devices and only one
oscillator is required. The devices which are not used for
the oscillator are put into the cascade mode by connecting
the A0/OSC pin to either VDD or VSS depending on the
required state for A0. In the cascade mode each
PCF8577C is synchronized from the backplane signal(s).
6.3 User-accessible registers
There are nine user-accessible 1-byte registers. The first
is a control register which is used to control the loading of
data into the segment byte registers and to select display
options. The other eight are segment byte registers, split
into two banks of storage, which store the segment data.
The set of even numbered segment byte registers is called
BANK A. Odd numbered segment byte registers are called
BANK B.
There is one slave address for the PCF8577C (see Fig.6).
All addressed devices load the second byte into the control
register and each device maintains an identical copy of the
control byte in the control register at all times (see I2C-bus
protocol, Fig.7), i.e. all addressed devices respond to
control commands sent on the I2C-bus.
The control register is shown in more detail in Fig.3.
The least-significant bits select which device and which
segment byte register is loaded next. This part of the
register is therefore called the Segment Byte Vector
(SBV).
The upper three bits of the SBV (V5 to V3) are compared
with the hardware subaddress input signals A2, A1
and A0. If they are the same then the device is enabled for
loading, if not the device ignores incoming data but
remains active.
The three least-significant bits of the SBV (V2 to V0)
address one of the segment byte registers within the
enabled chip for loading segment data.
The control register also has two display control bits.
These bits are named MODE and BANK. The MODE bit
selects whether the display outputs are configured for
direct or duplex drive displays. The BANK bit allows the
user to display BANK A or BANK B.
6.4 Auto-incremented loading
After each segment byte is loaded the SBV is incremented
automatically. Thus auto-incremented loading occurs if
more than one segment byte is received in a data transfer.
Since the SBV addresses both device and segment
registers in all addressed chips, auto-incremented loading
may proceed across device boundaries provided that the
hardware subaddresses are arranged contiguously.
1998 Jul 30
5
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| Information | Total 28 Pages | |
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