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PDF AD8016 Data sheet ( Hoja de datos )
| Número de pieza | AD8016 | |
| Descripción | High Output Current xDSL Line Driver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
xDSL line driver that features full ADSL central office (CO)
Performance on ±12 V supplies
Low power operation
±5 V to ±12 V voltage supply
12.5 mA/amp (typical) total supply current
Power reduced keep alive current of 4.5 mA/amp
High output voltage and current drive
IOUT = 600 mA
40 V p-p differential output voltage RL = 50 Ω, VS = ±12 V
Low single-tone distortion
–75 dBc @ 1 MHz SFDR, RL = 100 Ω, VOUT = 2 V p-p
MTPR = –75 dBc, 26 kHz to 1.1 MHz, ZLINE = 100 Ω,
PLINE = 20.4 dBm
High Speed
78 MHz bandwidth (–3 dB), G = +5
40 MHz gain flatness
1000 V/μs slew rate
GENERAL DESCRIPTION
The AD8016 high output current dual amplifier is designed for
the line drive interface in Digital Subscriber Line systems such
as ADSL, HDSL2, and proprietary xDSL systems. The drivers
are capable, in full-bias operation, of providing 24.4 dBm
output power into low resistance loads, enough to power a
20.4 dBm line, including hybrid insertion loss.
The AD8016 is available in a low cost 24-lead SOIC_W_BAT
and a 28-lead TSSOP_EP with an exposed lead frame (ePAD).
Operating from ±12 V supplies, the AD8016 requires only 1.5 W
of total power dissipation (refer to the Power Dissipation section
for details) while driving 20.4 dBm of power downstream using
Low Power, High Output
Current xDSL Line Driver
AD8016
PIN CONFIGURATIONS
+V1 1
24 +V2
VOUT1
VINN1
VINP1
AGND
2
3
4
5
AGND 6
AGND 7
AGND 8
23 VOUT2
–+ +–
22 VINN2
21 VINP2
20 AGND
AD8016 19 AGND
TOP VIEW
(Not to Scale) 18 AGND
17 AGND
PWDN0 9
16 PWDN1
DGND 10
15 BIAS
–V1 11
14 –V2
NC 12
13 NC
NC = NO CONNECT
Figure 1. 24-Lead SOIC_W_BAT (RB-24)
NC 1
NC 2
NC 3
+VIN2
–VIN2
VOUT2
+V2
4
5
6
7
+V1 8
VOUT1 9
–VIN1 10
+VIN1 11
NC 12
NC 13
NC 14
AD8016ARE
TOP VIEW
(Not to Scale)
28 NC
27 NC
26 NC
25 NC
24 PWDN1
23 BIAS
22 –V2
21 –V1
20 DGND
19 NC
18 PWDN0
17 NC
16 NC
15 NC
NOTES
1. THE EXPOSED PADDLE IS FLOATING,
NOT ELECTRICALLY CONNECTED
INTERNALLY.
2. NC = NO CONNECT.
Figure 2. 28-Lead TSSOP_EP (RE-28-1)
the xDSL hybrid in Figure 35 and Figure 36. Two digital bits
(PWDN0, PWDN1) allow the driver to be capable of full
performance, an output keep-alive state, or two intermediate
bias states. The keep-alive state biases the output transistors
enough to provide a low impedance at the amplifier outputs
for back termination.
The low power dissipation, high output current, high output
voltage swing, flexible power-down, and robust thermal
packaging enable the AD8016 to be used as the central office
(CO) terminal driver in ADSL, HDSL2, VDSL, and proprietary
xDSL systems.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
1 page  
AD8016
Data Sheet
@ 25°C, VS = ±6 V, RL = 100 Ω, PWDN0, PWDN1 = (1, 1), TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Peaking
Slew Rate
Rise and Fall Time
Settling Time
Input Overdrive Recovery Time
NOISE/DISTORTION PERFORMANCE
Distortion, Single-Ended
Second Harmonic
Third Harmonic
Multitone Power Ratio1
IMD
IP3
Voltage Noise (RTI)
Input Current Noise
INPUT CHARACTERISTICS
RTI Offset Voltage
+Input Bias Current
−Input Bias Current
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Quiescent Current
Recovery Time
Shutdown Current
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
Test Conditions/Comments
G = +1, RF = 1.5 kΩ, VOUT = 0.2 V p-p
G = +5, RF = 499 Ω, VOUT < 0.5 V p-p
G = +5, RF = 499 Ω, VOUT = 0.2 V p-p
VOUT = 1 V rms
VOUT = 0.2 V p-p < 50 MHz
VOUT = 4 V p-p, G = +2
VOUT = 2 V p-p
0.1%, VOUT = 2 V p-p
VOUT = 6.5 V p-p
G = +5, VOUT = 2 V p-p, RF = 499 Ω
fC = 1 MHz, RL = 100 Ω/25 Ω
fC = 1 MHz, RL = 100 Ω/25 Ω
26 kHz to 138 kHz, ZLINE = 100 Ω, PLINE = 13 dBm
500 kHz, Δf = 110 kHz, RL = 100 Ω/25 Ω
500 kHz
f = 10 kHz
f = 10 kHz
Single-Ended, RL = 100 Ω
G = +5, RL = 5 Ω, f = 100 kHz, −60 dBc SFDR
RS = 10 Ω
PWDN1, PWDN0 = (1, 1)
PWDN1, PWDN0 = (1, 0)
PWDN1, PWDN0 = (0, 1)
PWDN1, PWDN0 = (0, 0)
To 95% of IQ
250 μA out of bias pin
ΔVS = ±1 V
Min
70
10
−73/61
−80/−68
−87/−82
42/39
−3.0
−25
−30
−4
60
−5
300
63
−40
Typ
320
71
15
80
0.7
300
2
39
350
−75/−63
−82/−70
−68
−88/−83
42/39
4
17
0.2
10
10
400
2
66
420
830
50
8
6
4
3
23
1.0
80
1See Figure 48, R20, R21 = 0 Ω, R1 = open.
Max Unit
MHz
MHz
MHz
MHz
1.0 dB
V/μs
ns
ns
ns
dBc
dBc
dBc
dBc
dBm
5 nV/√Hz
20 pA√Hz
+3.0 mV
+25 μA
+30 μA
kΩ
pF
+4 V
dB
+5 V
mA
mA
pF
9.7 mA/Amp
6.9 mA/Amp
5.0 mA/Amp
4.1 mA/Amp
μs
2.0 mA/Amp
dB
+85 °C
LOGIC INPUTS (CMOS COMPATIBLE LOGIC)
PWDN0, PWDN1, VCC = ±12 V or ±6 V; full temperature range.
Table 3.
Parameter
Logic 1 Voltage
Logic 0 Voltage
Min
2.2
0
Typ
Max
VCC
0.8
Unit
V
V
Rev. C | Page 4 of 20
5 Page 
AD8016
11
G = +5
8
RL = 100Ω
RF = 499Ω
5
2
–1
–4
–7
–10
–13
–16
–19
1
10 100
FREQUENCY (MHz)
500
Figure 24. Output Voltage vs. Frequency; VS = ±12 V
20 VIN = 2V rms
10 RF = 602Ω
0
(1,1)
(1,0)
–10
–20
–30 (0,1)
–40
(0,0)
–50
–60
–70
–80
0.03 0.1
1 10
FREQUENCY (MHz)
100 500
Figure 25. CMRR vs. Frequency; VS = ±12 V @ PWDN1, PWDN0 Codes
6
3
0
(1,1)
–3
–6
–9 (1,0)
–12
(0,1)
–15
–18
–21
VIN = 40mV p-p
G = +5
–24 RL = 100Ω
1
10 100
FREQUENCY (MHz)
(0,0)
500
Figure 26. Frequency Response; VS = ±6 V, @ PWDN1, PWDN0 Codes
Data Sheet
11
G = +5
8
RL = 100Ω
RF = 499Ω
5
2
–1
–4
–7
–10
–13
–16
–19
1
10 100
FREQUENCY (MHz)
500
Figure 27. Output Voltage vs. Frequency; VS = ±6 V
–10
RF = 499Ω
–20
–30
+PSRR
–40
–50
–PSRR
–60
–70
–80
–90
0.01
0.1 1 10
FREQUENCY (MHz)
100
Figure 28. PSRR vs. Frequency; VS = ±12 V
500
180
160
140
120
100
80
60
40
20
0
10
+ INOISE
VIN NOISE
100
1k
10k 100k
1M
FREQUENCY (MHz)
Figure 29. Noise vs. Frequency
90
80
70
60
50
40
30
20
10
0
10M
Rev. C | Page 10 of 20
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet AD8016.PDF ] | |
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